EEE/CSC 120 HARDWARE LAB 2 ANSWER SHEET Operation of Adder and Comparator

EEE/CSC 120 HARDWARE LAB 2 ANSWER SHEET Operation of Adder and Comparator Name: ___Stone Thompson_______________________ Task 0-1: Building a HALF-ADDER Paste a copy of your half-adder timing diagram and your Verilog here. Please keep in mind, your timing waveform should include all the input combinations of A,B (0,0); (0,1); (1,0) and (1,1). Verilog: 1 This study source was downloaded by from CourseH on :48:28 GMT -06:00 WaveForm: 2 This study source was downloaded by from CourseH on :48:28 GMT -06:00 Task 0-2: Building the Three-Bit Full-Adder Paste a copy of your full-adder timing diagram and your Verilog here. Please keep in mind, your timing waveform should include all the input combinations of A,B,C (0,0,0); (0,0,1); (0,1,0); (0,1,1); (1,0,0); (1,0,1); (1,1,0) and (1,1,1). Please comment on any issues that you may have encountered. Verilog WaveForm 3 This study source was downloaded by from CourseH on :48:28 GMT