UNIT-I EC3552-VLSI AND CHIP DESIGN
UNIT I - MOS TRANSISTOR PRINCIPLES
MOS logic families (NMOS and CMOS), Ideal and Non Ideal IV Characteristics, CMOS devices,
MOS(FET) Transistor Characteristic under Static and Dynamic Conditions, Technology Scaling, power
consumption
1.1: INTRODUCTION: (VLSI)
In 1958, Jack Kilby built the first integrated circuit flip-flop at Texas Instruments.
Bell Labs developed the bipolar junction transistor. Bipolar transistors were more reliable, less
noisy and more power-efficient.
In 1960s, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) began to enter in
the production.
MOSFETs offer the compelling advantage that; they draw almost zero control current while
idle.
They come in two flavors: nMOS and pMOS, using n-type and p-type silicon respectively.
In 1963, Frank Wanlass at Fairchild described the first logic gates using MOSFETs.
Fairchild’s gates used both nMOS and pMOS transistors, naming as Complementary Metal
Oxide Semiconductor (CMOS).
Power consumption became a major issue in the 1980s as hundreds of thousands of transistors
were integrated onto a single die.
CMOS processes were widely adopted and replaced nMOS and bipolar processes for all
digital logic applications.
In 1965, Gordon Moore observed that plotting the number of transistors that can be most
economically manufactured on a chip gives a straight line on a semi logarithmic scale.
o Moore’s Law is defined as transistor count doubling every 18 months.
The level of integration of chips is classified as
Small Scale Integration (SSI)
Medium Scale Integration (MSI)
Large Scale Integration (LSI)
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, UNIT-I EC3552-VLSI AND CHIP DESIGN
Very Large Scale Integration (VLSI)
Ultra Large Scale Integration (ULSI)
Small scale Integration:
Small-Scale Integration (SSI) circuits have less than 10 gates. Example: 7404 inverter.
Medium scale Integration:
Medium-Scale Integration (MSI) circuits have up to 1000 gates. Example: 74161 counter.
Large scale Integration:
Large-Scale Integration (LSI) circuits have up to 10,000 gates. Example: 8-bit microprocessor
(8085).
Very large scale Integration:
Very large scale Integration (VLSI) with gates counting up to lakhs. Example: 16-bit
microprocessor (8086).
The feature size of a CMOS manufacturing process refers to the minimum dimension of a
transistor that can be reliably built.
Ultra large scale Integration:
Ultra Large-Scale Integration (ULSI) is the process of integrating millions of transistors on a
single silicon semiconductor microchip.
***********************************************************************************
1.2: MOS Transistor
nMOS and pMOS transistor
Explain the basic concept of nMOS and pMOS transistor with relevant symbol.
A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing layers of
conducting and insulating materials.
CMOS technology provides two types of transistors. They are n-type transistor (nMOS) and p-
type transistor (pMOS).
As transistor operation is controlled by electric fields, the devices are also called Metal Oxide
Semiconductor Field Effect Transistors (MOSFETs).
The transistor consists of a stack of the conducting gate, an insulating layer of silicon dioxide
(SiO2) and the silicon wafer, also called as substrate, body or bulk.
A pMOS transistor consists of p-type source and drain region with an n-type body.
An nMOS transistor consists of n-type source and drain region with a p-type body.
Figure 1: (a) n-MOS transistor (b) p-MOS transistor
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, UNIT-I EC3552-VLSI AND CHIP DESIGN
nMOS Transistor:
In an nMOS transistor, the body is grounded and the p–n junction of the source and drain to
body are reverse-biased.
As the gate is grounded, no current flows through junction. Hence, the transistor is OFF.
If the gate voltage is raised, it creates an electric field, that start to attract free electrons to
the underside of the Si–SiO2 interface.
If the voltage is raised more, a thin region under the gate called the channel is inverted.
Since a conducting path of electron carriers is formed from source to drain, current starts to
flow. So, the transistor is said to be ON.
pMOS Transistor:
For a pMOS transistor, the body is held at a positive voltage.
When the gate terminal has a positive voltage, the source and drain junctions are reverse-
biased and no current flows. So, the transistor is said to OFF.
When the gate voltage is lowered, positive charges are attracted to the underside of the Si–
SiO2 interface.
When a sufficient low gate voltage is applied, the channel inverts and a conducting path of
positive carriers is formed from source to drain, which makes the transistor ON.
NOTE:
The symbol for the pMOS transistor has a bubble on the gate, indicating that the transistor
behavior is opposite to nMOS.
When the gate of an nMOS transistor is 1, the transistor is ON. When the gate is 0, the nMOS
transistor is OFF.
A pMOS transistor is ON when the gate is low(0) and OFF when the gate is high(1).
1.3: Modes of MOS TRANSISTOR
Explain the accumulation (Enhancement) mode, depletion layer and inversion layer of
MOS transistor with diagram.
The MOS transistor is a majority-carrier device, in which the current in a conducting channel
is controlled by gate voltage.
In an nMOS transistor, the majority carriers are electrons.
In a pMOS transistor, the majority carriers are holes.
Figure 2 shows a simple MOS structure. The top layer of the structure is a good conductor
called the gate.
Transistor gate is polysilicon, i.e., silicon formed from many small crystals. The middle layer
is a very thin insulating film of SiO2, called the gate oxide. The bottom layer is the doped
silicon body.
The figure 2 shows a p-type body, in which the carriers are holes. The body is grounded and
voltage is applied to the gate.
The gate oxide is a good insulator, so almost zero current flows from the gate to the body.
Accumulation (Enhancement) mode:
In Figure 2(a), when a negative voltage is applied to the gate, negative charges are formed on
the gate.
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, UNIT-I EC3552-VLSI AND CHIP DESIGN
The positively charged holes are attracted to the region under the gate. This is called the
accumulation mode.
Depletion mode:
In Figure 2(b), when a small positive voltage is applied to the gate, positive charges are
formed on the gate.
The holes in the body are repelled from the region directly under the gate, resulting in a
depletion region forming below the gate.
Inversion layer:
In Figure 2(c), when a higher positive potential greater than threshold voltage (Vt) is applied,
more positive charges are attracted to the gate.
The holes are repelled and some free electrons in the body are attracted to the region under the
gate. This conductive layer of electrons in the p-type body is called the inversion layer.
The threshold voltage depends on the number of dopants in the body and the thickness tox of
the oxide.
Figure 2: MOS structure demonstrating (a) accumulation, (b) depletion, and (c) inversion layer
1.4: Operating regions of MOS transistor:
Draw the small signal model of device during cut-off, linear and saturation. (April 2018)
Discuss the cutoff, linear and saturation region operation of MOS transistor. (Nov 2009)
The MOS transistor operates in cutoff region, linear region and saturation region.
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UNIT I - MOS TRANSISTOR PRINCIPLES
MOS logic families (NMOS and CMOS), Ideal and Non Ideal IV Characteristics, CMOS devices,
MOS(FET) Transistor Characteristic under Static and Dynamic Conditions, Technology Scaling, power
consumption
1.1: INTRODUCTION: (VLSI)
In 1958, Jack Kilby built the first integrated circuit flip-flop at Texas Instruments.
Bell Labs developed the bipolar junction transistor. Bipolar transistors were more reliable, less
noisy and more power-efficient.
In 1960s, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) began to enter in
the production.
MOSFETs offer the compelling advantage that; they draw almost zero control current while
idle.
They come in two flavors: nMOS and pMOS, using n-type and p-type silicon respectively.
In 1963, Frank Wanlass at Fairchild described the first logic gates using MOSFETs.
Fairchild’s gates used both nMOS and pMOS transistors, naming as Complementary Metal
Oxide Semiconductor (CMOS).
Power consumption became a major issue in the 1980s as hundreds of thousands of transistors
were integrated onto a single die.
CMOS processes were widely adopted and replaced nMOS and bipolar processes for all
digital logic applications.
In 1965, Gordon Moore observed that plotting the number of transistors that can be most
economically manufactured on a chip gives a straight line on a semi logarithmic scale.
o Moore’s Law is defined as transistor count doubling every 18 months.
The level of integration of chips is classified as
Small Scale Integration (SSI)
Medium Scale Integration (MSI)
Large Scale Integration (LSI)
1
, UNIT-I EC3552-VLSI AND CHIP DESIGN
Very Large Scale Integration (VLSI)
Ultra Large Scale Integration (ULSI)
Small scale Integration:
Small-Scale Integration (SSI) circuits have less than 10 gates. Example: 7404 inverter.
Medium scale Integration:
Medium-Scale Integration (MSI) circuits have up to 1000 gates. Example: 74161 counter.
Large scale Integration:
Large-Scale Integration (LSI) circuits have up to 10,000 gates. Example: 8-bit microprocessor
(8085).
Very large scale Integration:
Very large scale Integration (VLSI) with gates counting up to lakhs. Example: 16-bit
microprocessor (8086).
The feature size of a CMOS manufacturing process refers to the minimum dimension of a
transistor that can be reliably built.
Ultra large scale Integration:
Ultra Large-Scale Integration (ULSI) is the process of integrating millions of transistors on a
single silicon semiconductor microchip.
***********************************************************************************
1.2: MOS Transistor
nMOS and pMOS transistor
Explain the basic concept of nMOS and pMOS transistor with relevant symbol.
A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing layers of
conducting and insulating materials.
CMOS technology provides two types of transistors. They are n-type transistor (nMOS) and p-
type transistor (pMOS).
As transistor operation is controlled by electric fields, the devices are also called Metal Oxide
Semiconductor Field Effect Transistors (MOSFETs).
The transistor consists of a stack of the conducting gate, an insulating layer of silicon dioxide
(SiO2) and the silicon wafer, also called as substrate, body or bulk.
A pMOS transistor consists of p-type source and drain region with an n-type body.
An nMOS transistor consists of n-type source and drain region with a p-type body.
Figure 1: (a) n-MOS transistor (b) p-MOS transistor
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, UNIT-I EC3552-VLSI AND CHIP DESIGN
nMOS Transistor:
In an nMOS transistor, the body is grounded and the p–n junction of the source and drain to
body are reverse-biased.
As the gate is grounded, no current flows through junction. Hence, the transistor is OFF.
If the gate voltage is raised, it creates an electric field, that start to attract free electrons to
the underside of the Si–SiO2 interface.
If the voltage is raised more, a thin region under the gate called the channel is inverted.
Since a conducting path of electron carriers is formed from source to drain, current starts to
flow. So, the transistor is said to be ON.
pMOS Transistor:
For a pMOS transistor, the body is held at a positive voltage.
When the gate terminal has a positive voltage, the source and drain junctions are reverse-
biased and no current flows. So, the transistor is said to OFF.
When the gate voltage is lowered, positive charges are attracted to the underside of the Si–
SiO2 interface.
When a sufficient low gate voltage is applied, the channel inverts and a conducting path of
positive carriers is formed from source to drain, which makes the transistor ON.
NOTE:
The symbol for the pMOS transistor has a bubble on the gate, indicating that the transistor
behavior is opposite to nMOS.
When the gate of an nMOS transistor is 1, the transistor is ON. When the gate is 0, the nMOS
transistor is OFF.
A pMOS transistor is ON when the gate is low(0) and OFF when the gate is high(1).
1.3: Modes of MOS TRANSISTOR
Explain the accumulation (Enhancement) mode, depletion layer and inversion layer of
MOS transistor with diagram.
The MOS transistor is a majority-carrier device, in which the current in a conducting channel
is controlled by gate voltage.
In an nMOS transistor, the majority carriers are electrons.
In a pMOS transistor, the majority carriers are holes.
Figure 2 shows a simple MOS structure. The top layer of the structure is a good conductor
called the gate.
Transistor gate is polysilicon, i.e., silicon formed from many small crystals. The middle layer
is a very thin insulating film of SiO2, called the gate oxide. The bottom layer is the doped
silicon body.
The figure 2 shows a p-type body, in which the carriers are holes. The body is grounded and
voltage is applied to the gate.
The gate oxide is a good insulator, so almost zero current flows from the gate to the body.
Accumulation (Enhancement) mode:
In Figure 2(a), when a negative voltage is applied to the gate, negative charges are formed on
the gate.
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, UNIT-I EC3552-VLSI AND CHIP DESIGN
The positively charged holes are attracted to the region under the gate. This is called the
accumulation mode.
Depletion mode:
In Figure 2(b), when a small positive voltage is applied to the gate, positive charges are
formed on the gate.
The holes in the body are repelled from the region directly under the gate, resulting in a
depletion region forming below the gate.
Inversion layer:
In Figure 2(c), when a higher positive potential greater than threshold voltage (Vt) is applied,
more positive charges are attracted to the gate.
The holes are repelled and some free electrons in the body are attracted to the region under the
gate. This conductive layer of electrons in the p-type body is called the inversion layer.
The threshold voltage depends on the number of dopants in the body and the thickness tox of
the oxide.
Figure 2: MOS structure demonstrating (a) accumulation, (b) depletion, and (c) inversion layer
1.4: Operating regions of MOS transistor:
Draw the small signal model of device during cut-off, linear and saturation. (April 2018)
Discuss the cutoff, linear and saturation region operation of MOS transistor. (Nov 2009)
The MOS transistor operates in cutoff region, linear region and saturation region.
4
