Digital Fundamentals – Test Bank, 11th Edition by Thomas Floyd, All Chapters

Test Bank for Digital
Fundamentals, 11e
Thomas Floyd (All
Chapters,)

, Chapter 1

Name___________________________________



MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the
question.
1) Which circuit converts data from serial form to parallel form? 1) _______
A) Multiplexer B) Comparator C) E ncoder D)
Demultiplexer


2) Which one of the circuits listed is made up of flip -flops? 2) _______
A) A comparator B) A converter C) A register D) A
multiplexer

3) The time from one leading edge on a digital waveform to the next is the waveform ________. 3) _______
A) rise time B) pulse width C) period D) fall time




Figure 1-1


4) The time between transition 1 and transition 3 in Figure 1 -1 is the ________. 4) _______
A) period B) frequency C) amplitude D) pulse
width


5) The output from an OR gate is HIGH ________. 5) _______
A) when at least one input is HIGH B) only when all inputs are HIGH
C) only when all inputs are LOW D) none of the above




Figure 1-3


6) The symbol in Figure 1 -3(B) represents the ________ function. 6) _______
A) OR B) NON C) XOR D) AND

, ______
7) On a positive -going pulse, the leading edge is the ________. 7) _______
A) HIGH -to-LOW transition B) falling edge C) negative -going edge
D) positive -going edge

8) Of the circuits listed, the one that is most likely to be found in a CD player is a(n) ________. 8) _______
A) programmable logic device B) digital -to-analog converter C) analog -to-digital
converter D) SPLD




Figure 1-1



9) Which edge in Figure 1 -1 is the trailing edge? 9) _______
A) 1 B) 2 C) 3 D) Both 1 and 3
10) The arrow in the figure below points to pin ________. 10)




A) 17 B) 16 C) 5 D) 4

11) On a negative -going pulse, the leading edge is the ________. 11) ______
A) LOW -to-HIGH transition B) negative -going edge C) positive -going edge D)
rising edge


12) Which circuit converts coded information into a noncoded form? 12) ______
A) Comparator B) Encoder C) Decoder D) Mult iplexer




Figure 1-3


13) The symbol in Figur e 1-3(C) represents the ________ function. 13) ______
A) XOR B) NOT C) OR D) AND

, 14) The a pproximate duty cycle for the digital waveform below is ________. 14) ______



A) 20 % B) 80 % C) 30 % D) 50 %




Figure 1-4


15) The package style in Figure 1 -4(C) is a(n) ________. 15) ______
A) SOIC B) PLCC C) LCCC D) FP

16) The output from an OR gate is LOW ________. 16) ______
A) only when all inputs are LOW B) whenever any input is HIGH
C) only when all inputs are HIGH D) none of the above

17) The netlist is generated during the ________ phase of the PLD programming process. 17) ______
A) design entry B) compilation C) synthesis D) do wnload