IS310 Exam 1 2026 Questions and Answers (160 Questions) – Computer Organization, Computer Architecture, IEEE-754, Digital Logic & Assembly – UMBC

This document contains 160 verified exam questions and answers for IS310 Exam #1 (2026) at UMBC, covering foundational concepts in computer organization, computer architecture, number systems, digital logic, memory, buses, CPU structure, and low-level programming. The material explains the distinction between computer organization and computer architecture, the Instruction Set Architecture (ISA), Von Neumann architecture and bottleneck, Moore’s Law and Rock’s Law, and the historical evolution of computing from vacuum tubes to integrated circuits and VLSI. The document provides in-depth coverage of data representation, including binary conversion methods, signed-magnitude representation, one’s complement, two’s complement, radix complement systems, overflow, bias and excess notation, IEEE-754 single and double precision floating-point formats, normalization, floating-point errors, range, precision, and accuracy. It also examines character encoding systems such as ASCII, Extended ASCII, Unicode, and Binary-Coded Decimal (BCD), along with systematic error detection methods including parity, checksum, CRC, Hamming codes, and Reed-Solomon codes. Extensive focus is given to digital logic and circuit design, including Boolean algebra, Boolean functions, duality principle, sum-of-products and product-of-sums forms, Karnaugh maps, combinational logic, sequential circuits, flip-flops, finite-state machines (Moore and Mealy machines), adders, decoders, multiplexers, parity generators, and digital synthesis versus digital analysis. The document also covers CPU components such as the ALU, control unit, datapath, registers, program counter, instruction register, status register, memory-address register, and memory-buffer register. Additional topics include system buses (data, control, and address lines), synchronous and asynchronous buses, clock frequency and cycle time, memory interleaving, fetch-decode-execute cycle, interrupts (maskable and non-maskable), interrupt service routines, assembly language, assembler directives, mnemonics, symbol tables, and branching instructions. Cloud computing models (SaaS, PaaS, IaaS), IoT, SCADA systems, cyber warfare, and embedded systems are also introduced to connect hardware fundamentals with modern computing environments. This resource is especially suitable for: Students enrolled in IS310 Computer Organization and Architecture Computer science and information systems majors Electrical and computer engineering students Students preparing for midterm or foundational architecture examinations Learners reviewing digital logic, assembly language, and data representation It serves as a comprehensive and structured exam preparation guide that consolidates theoretical foundations, hardware-level concepts, and low-level programming principles into a single, well-organized study resource. Keywords: computer organization, computer architecture, instruction set architecture, von neumann architecture, moores law, rocks law, ieee 754, floating point representation, twos complement, ones complement, signed magnitude, binary conversion, overflow, ascii encoding, unicode, binary coded decimal, checksum, cyclic redundancy check, hamming codes, boolean algebra, karnaugh map, combinational logic, sequential circuits, flip flop, finite state machine, cpu architecture, arithmetic logic unit, datapath, system bus, synchronous bus, asynchronous bus, memory interleaving, fetch decode execute cycle, interrupts, assembly language, assembler, cloud computing models