ECEN 449/749 Spring 2025: Final Exam May 5, 2025
NAME_______________________ UIN_____________________
Final Exam
ECEN 449/749
May 5, 2025
1. (34% Undergrad / 25% Grad) Given the simplified FPGA in Figure 1, answer parts (a)
– (e) below. The registers/flip-flops have sequential delay, tp(seq) = 0.5 ns, set-up time,
tsu = 0.05 ns, and hold time, th = 0.1 ns, where 1 ns = 10-9 seconds. Each LUT in
Figure 1 has a combinational delay tp(comb) = 0.1 ns. Each of the LUT’s in Figure 1 has
a number between 1 and 15, which is used in part (e) to identify a particular LUT.
Figure 1 – Simplified FPGA LUT Diagram
1
, ECEN 449/749 Spring 2025: Final Exam May 5, 2025
(a) (6% Undergrad / 5% Grad) What is the maximum combinational delay from the output
of the input register to d1, d2, and d3 (don’t include tp(seq) or tsu as this part is only
combinational delay)? Assume wire delays between LUTs are 0 ns for this part.
tp(d1) = __________________________________________________
tp(d2) = __________________________________________________
tp(d3) = __________________________________________________
(b) (7% Undergrad / 5% Grad) Based on your results in part (a), what is the maximum
clock frequency of the circuit in Figure 1 in MHz? Show your work for partial credit.
(c) (7% Undergrad / 5% Grad) Assume the switch matrix plus wire combinational delay
when connecting from one LUT to an adjacent LUT is 0.05 ns. For this part, assume
an adjacent LUT is any one of the eight LUTs shown in Figure 2 below.
If you must connect to a LUT that is further away, assume you incur an additional
0.05 ns for each hop in the same row. If you must connect to a row above or below,
assume you take the faster diagonal path to get to the row above or below if available.
For example, if you need to go down one row and then two columns to the left, the
delay will be 2 x 0.05 ns (i.e., diagonal row down left and then one column left) and
not 3 x 0.05 ns (i.e., down row and then two columns left). Also assume there is 0.05
ns delay from the output of the input register to the first LUT and 0.05 ns delay from
the last LUT to the output register. What is the maximum combinational delay to
d1, d2, and d3 including the wire delays (i.e., combinational delay + wire delay).
You need to compare the total delays at the inputs to each LUT to determine the
worst case delay at the output of a LUT,
e.g., (2 LUT + 2 Wire) delays = 0.3 ns < (1 LUT + 5 Wire) = 0.35 ns.
Figure 2 – Adjacent LUT’s
2
NAME_______________________ UIN_____________________
Final Exam
ECEN 449/749
May 5, 2025
1. (34% Undergrad / 25% Grad) Given the simplified FPGA in Figure 1, answer parts (a)
– (e) below. The registers/flip-flops have sequential delay, tp(seq) = 0.5 ns, set-up time,
tsu = 0.05 ns, and hold time, th = 0.1 ns, where 1 ns = 10-9 seconds. Each LUT in
Figure 1 has a combinational delay tp(comb) = 0.1 ns. Each of the LUT’s in Figure 1 has
a number between 1 and 15, which is used in part (e) to identify a particular LUT.
Figure 1 – Simplified FPGA LUT Diagram
1
, ECEN 449/749 Spring 2025: Final Exam May 5, 2025
(a) (6% Undergrad / 5% Grad) What is the maximum combinational delay from the output
of the input register to d1, d2, and d3 (don’t include tp(seq) or tsu as this part is only
combinational delay)? Assume wire delays between LUTs are 0 ns for this part.
tp(d1) = __________________________________________________
tp(d2) = __________________________________________________
tp(d3) = __________________________________________________
(b) (7% Undergrad / 5% Grad) Based on your results in part (a), what is the maximum
clock frequency of the circuit in Figure 1 in MHz? Show your work for partial credit.
(c) (7% Undergrad / 5% Grad) Assume the switch matrix plus wire combinational delay
when connecting from one LUT to an adjacent LUT is 0.05 ns. For this part, assume
an adjacent LUT is any one of the eight LUTs shown in Figure 2 below.
If you must connect to a LUT that is further away, assume you incur an additional
0.05 ns for each hop in the same row. If you must connect to a row above or below,
assume you take the faster diagonal path to get to the row above or below if available.
For example, if you need to go down one row and then two columns to the left, the
delay will be 2 x 0.05 ns (i.e., diagonal row down left and then one column left) and
not 3 x 0.05 ns (i.e., down row and then two columns left). Also assume there is 0.05
ns delay from the output of the input register to the first LUT and 0.05 ns delay from
the last LUT to the output register. What is the maximum combinational delay to
d1, d2, and d3 including the wire delays (i.e., combinational delay + wire delay).
You need to compare the total delays at the inputs to each LUT to determine the
worst case delay at the output of a LUT,
e.g., (2 LUT + 2 Wire) delays = 0.3 ns < (1 LUT + 5 Wire) = 0.35 ns.
Figure 2 – Adjacent LUT’s
2
