ESE 5760 Memory questions and answers
Graded A+
Logical Effort
input capacitance of the gate / Input capacitance of an inverter (for equal drive); Quantifies
how hard a logic gate is to drive compared to an ideal inverter, assuming the same output drive
strength; 2-input NAND: g≈4/3 or 2-input NOR: g≈5/3
Path Logical Effort
The products of the logical efforts of each stage along the path; If the path has "hard" gates
(like NANDs) instead of simple inverters, G gets bigger and the path is inherently slower.
Path Electrical Effort
How much load the path has to drive; H = input capacitance of the first gate / output load
capacitance
Path Effort
Path Logical Effort * Path Electrical Effort; How "hard" the entire path is to drive
Branching Effort
The ratio of the total capacitance seen by a stage to the
capacitance on the path
γ
Internal device parasitics (there is no off-path load)
Propagation delay time
Maximum time from the input crossing 50% to the output crossing 50%
Contamination delay time
Minimum time from the input crossing 50% to the output crossing 50%; The fastest that the
gate might switch
Rise time
Time for a waveform to rise from 20% to 80% of its steady-state value
Fall time
Time for a waveform to fall from 80% to 20% of its steady-state value
,Slack
Difference between required and arrival times
P-type
Positive-type (because the majority carriers are positive holes)
N-type
Negative-type (because the majority carriers are negative electrons)
N+
Heavily doped n-type (we have a higher concentration of e-)
P+
Heavily doped p-type
pMOS transistor has approximately twice the resistance of the nMOS transistor
Because holes have lower mobility than electrons
Cell Density
The number of memory cells per unit area (e.g., F² per cell or cells per mm²), regardless of how
many bits each cell stores.
Bit Density
The number of stored bits per unit area (bits per mm²), accounting for how many bits each cell
can hold.
Latency
Time from data request to data ready, units usually in ps to µs.
Bandwidth
Amount of data that can be output per unit time
Bitwidth
The width of an interface. Usually reported in bits or B
Energy
Reported at various granularity and various levels of the memory (e.g.,
cell read energy vs. array read energy). Units are usually pJ/bit or pJ/word .
Retention
, How long one can still read the correct value from the data after it was written
Endurance
How many times a memory cell can be written before failure.
Non-Volatile
Retains data without power being supplied to the cell; Contains a hysteresis loop
Semi-Volatile
Long retention period, but will eventually lose data
Volatile
Loses data when power is removed
Static Cells
Memory is retained without any update (static power is consumed)
Dynamic Cells
Must be refreshed to retain data (refresh power consumed)
Random-Access Memory
Arbitrary address can be read at same speed
Sequential-Access Memory
Access memory in chunks of contiguous addresses.
Also called block-access
Content-Addressable Memory
Find address based on contents, e.g., search where data matches specific bit pattern. This is
important for cache.
Memory
Temporary, fast-access hardware used to actively hold data the processor is currently working
on (the "working set"), with frequent reads and writes.
Storage
Long-term, slower hardware used to retain data persistently (files, backups, archives), accessed
far less frequently.
Hysteresis
Graded A+
Logical Effort
input capacitance of the gate / Input capacitance of an inverter (for equal drive); Quantifies
how hard a logic gate is to drive compared to an ideal inverter, assuming the same output drive
strength; 2-input NAND: g≈4/3 or 2-input NOR: g≈5/3
Path Logical Effort
The products of the logical efforts of each stage along the path; If the path has "hard" gates
(like NANDs) instead of simple inverters, G gets bigger and the path is inherently slower.
Path Electrical Effort
How much load the path has to drive; H = input capacitance of the first gate / output load
capacitance
Path Effort
Path Logical Effort * Path Electrical Effort; How "hard" the entire path is to drive
Branching Effort
The ratio of the total capacitance seen by a stage to the
capacitance on the path
γ
Internal device parasitics (there is no off-path load)
Propagation delay time
Maximum time from the input crossing 50% to the output crossing 50%
Contamination delay time
Minimum time from the input crossing 50% to the output crossing 50%; The fastest that the
gate might switch
Rise time
Time for a waveform to rise from 20% to 80% of its steady-state value
Fall time
Time for a waveform to fall from 80% to 20% of its steady-state value
,Slack
Difference between required and arrival times
P-type
Positive-type (because the majority carriers are positive holes)
N-type
Negative-type (because the majority carriers are negative electrons)
N+
Heavily doped n-type (we have a higher concentration of e-)
P+
Heavily doped p-type
pMOS transistor has approximately twice the resistance of the nMOS transistor
Because holes have lower mobility than electrons
Cell Density
The number of memory cells per unit area (e.g., F² per cell or cells per mm²), regardless of how
many bits each cell stores.
Bit Density
The number of stored bits per unit area (bits per mm²), accounting for how many bits each cell
can hold.
Latency
Time from data request to data ready, units usually in ps to µs.
Bandwidth
Amount of data that can be output per unit time
Bitwidth
The width of an interface. Usually reported in bits or B
Energy
Reported at various granularity and various levels of the memory (e.g.,
cell read energy vs. array read energy). Units are usually pJ/bit or pJ/word .
Retention
, How long one can still read the correct value from the data after it was written
Endurance
How many times a memory cell can be written before failure.
Non-Volatile
Retains data without power being supplied to the cell; Contains a hysteresis loop
Semi-Volatile
Long retention period, but will eventually lose data
Volatile
Loses data when power is removed
Static Cells
Memory is retained without any update (static power is consumed)
Dynamic Cells
Must be refreshed to retain data (refresh power consumed)
Random-Access Memory
Arbitrary address can be read at same speed
Sequential-Access Memory
Access memory in chunks of contiguous addresses.
Also called block-access
Content-Addressable Memory
Find address based on contents, e.g., search where data matches specific bit pattern. This is
important for cache.
Memory
Temporary, fast-access hardware used to actively hold data the processor is currently working
on (the "working set"), with frequent reads and writes.
Storage
Long-term, slower hardware used to retain data persistently (files, backups, archives), accessed
far less frequently.
Hysteresis
