Digital Design and Computer Architecture ARM
Edition (2016) – Solutions Manual – by Harris
In digital design, how does behavioral modeling differ from structural modeling? - answer-
Behavioral modeling describes what a circuit does (functionality), while structural modeling
describes how it is built (gate interconnections).
What is the primary cause of a glitch in a combinational logic circuit? - answer-A single input
variable change that crosses the boundary between two prime implicants in a Karnaugh map.
How can a designer eliminate glitches in a combinational circuit using a Karnaugh map? -
answer-By adding redundant implicants to cover the boundaries between existing prime
implicants.
The time interval required for a signal to settle at a register input before the clock edge is
known as the \_\_\_\_\_. - answer-Setup time (\$t\_\{setup\}\$)
Why is the hold time (\$t\_\{hold\}\$) excluded from the calculation of the minimum clock
period (\$T\_c\$)? - answer-Hold time ensures data stability after the clock edge and does not
limit the speed of the combinational path.
In submicron designs (under \$0.18 <\\mu m\$>), what factor plays the dominant role in
determining interconnect performance? - answer-Interconnect delay (routing-dependent delay)
Which FSM model produces outputs that are a function of both the present state and the
current inputs? - answer-Mealy machine
How does a Moore machine's output logic differ from a Mealy machine's output logic? -
1
, answer-Moore machine outputs depend strictly on the present state, whereas Mealy outputs
depend on both state and inputs.
What is the risk of using an incomplete sensitivity list in a Verilog level-sensitive 'always' block? -
answer-It may result in the synthesis tool inferring unintended memory (latches).
In the context of metastability, what is the relationship between recovery time and the
probability of failure? - answer-The probability of failure decreases exponentially as the time
available for recovery increases.
What is the specific purpose of a 'Synchronizer' in a digital system? - answer-To reduce the
effects of metastability when signals cross asynchronous clock domains.
Formula: Minimum clock period (\$T\_c\$) for a synchronous circuit. - answer-\$T\_c <\\ge t\_
\{pcq\}> + t\_\{pd\} + t\_\{setup\}\$
In a RISC-V architecture, in which direction does the stack grow in memory? - answer-It grows
downward toward lower memory addresses.
What is the primary difference between 'Spatial Parallelism' and 'Temporal Parallelism'? -
answer-Spatial parallelism uses multiple hardware copies to process data, while temporal
parallelism (pipelining) overlaps steps of a process over time.
In computer memory management, what is the primary benefit of 'Virtual Memory'? - answer-It
provides memory protection by giving each program its own private virtual address space.
What determines the 'Latency' of a digital system? - answer-The time required for a single
token to pass through the system from start to end.
2
Edition (2016) – Solutions Manual – by Harris
In digital design, how does behavioral modeling differ from structural modeling? - answer-
Behavioral modeling describes what a circuit does (functionality), while structural modeling
describes how it is built (gate interconnections).
What is the primary cause of a glitch in a combinational logic circuit? - answer-A single input
variable change that crosses the boundary between two prime implicants in a Karnaugh map.
How can a designer eliminate glitches in a combinational circuit using a Karnaugh map? -
answer-By adding redundant implicants to cover the boundaries between existing prime
implicants.
The time interval required for a signal to settle at a register input before the clock edge is
known as the \_\_\_\_\_. - answer-Setup time (\$t\_\{setup\}\$)
Why is the hold time (\$t\_\{hold\}\$) excluded from the calculation of the minimum clock
period (\$T\_c\$)? - answer-Hold time ensures data stability after the clock edge and does not
limit the speed of the combinational path.
In submicron designs (under \$0.18 <\\mu m\$>), what factor plays the dominant role in
determining interconnect performance? - answer-Interconnect delay (routing-dependent delay)
Which FSM model produces outputs that are a function of both the present state and the
current inputs? - answer-Mealy machine
How does a Moore machine's output logic differ from a Mealy machine's output logic? -
1
, answer-Moore machine outputs depend strictly on the present state, whereas Mealy outputs
depend on both state and inputs.
What is the risk of using an incomplete sensitivity list in a Verilog level-sensitive 'always' block? -
answer-It may result in the synthesis tool inferring unintended memory (latches).
In the context of metastability, what is the relationship between recovery time and the
probability of failure? - answer-The probability of failure decreases exponentially as the time
available for recovery increases.
What is the specific purpose of a 'Synchronizer' in a digital system? - answer-To reduce the
effects of metastability when signals cross asynchronous clock domains.
Formula: Minimum clock period (\$T\_c\$) for a synchronous circuit. - answer-\$T\_c <\\ge t\_
\{pcq\}> + t\_\{pd\} + t\_\{setup\}\$
In a RISC-V architecture, in which direction does the stack grow in memory? - answer-It grows
downward toward lower memory addresses.
What is the primary difference between 'Spatial Parallelism' and 'Temporal Parallelism'? -
answer-Spatial parallelism uses multiple hardware copies to process data, while temporal
parallelism (pipelining) overlaps steps of a process over time.
In computer memory management, what is the primary benefit of 'Virtual Memory'? - answer-It
provides memory protection by giving each program its own private virtual address space.
What determines the 'Latency' of a digital system? - answer-The time required for a single
token to pass through the system from start to end.
2
