Register File, RISC Instruction Set, Immediate and Register Addressing,
Stack and Heap Memory Management, Arithmetic and Logical
Operations, Branching (bne), Jump-and-Link (jal), Shift Instructions
(sll/srl), Sign Bit and 2’s Complement, Word-Level Data,
Synchronization, Multi-Processor Access, Store-Conditional (sc),
Binary-to-Decimal Conversion, Common Case Optimization, Clock
Cycles, Instruction Throughput, Latency, Pipelining, Forwarding, Cache
Memory Hierarchy (L1/L2), Dynamic and Static Relocation, Virtual
Memory, Process Life Cycle, PCB, Context Switching, Multi-Level
Feedback Queues, CPU Performance Metrics, SPEC Benchmarks, ARM
RISC Architecture Exam Questions Verified and Provided with
Complete A+ Graded Rationales Latest Updated 2026
MIPS
millions of instructions per second
a gets b + c
add a, b, c
Design Principle 1
Simplicity favors regularity
, f = (g+h) - (i + j)
add t0, s1, s2
add t1, s3, s4
sub f, t0, ti
MIPS has a ___ x ___ bit register file
32 x 32
A "word"
32-bit data
Design Principle 2
Smaller is faster
With immediate instruction, there is no ______operation
Subtraction
Design Principle 3
Make the common case fast