CEA 201 Practice Test (2026) | Chamberlain Computer Architecture Q&A (PDF), Exams of Architecture

CEA 201 Practice Test (2026) | Chamberlain
Computer Architecture Q&A (PDF), Exams of
Architecture


Section 1: Digital Logic & Number Systems (Questions 1–25)

1. Convert the binary number 11011010₂ to decimal.

A) 210

B) 218

C) 202

D) 194

Answer: B) 218

Rationale: 11011010₂ = 1×2⁷ + 1×2⁶ + 0×2⁵ + 1×2⁴ + 1×2³ + 0×2² + 1×2¹ + 0×2⁰ =

128 + 64 + 0 + 16 + 8 + 0 + 2 + 0 = 218.




2. Convert the decimal number 157 to hexadecimal.

A) 9D₁₆

B) 9E₁₆

C) 8D₁₆

D) A9₁₆

,Answer: A) 9D₁₆

Rationale: 157 ÷ 16 = 9 remainder 13 (D). So 157₁₀ = 9D₁₆.




3. Which of the following is the two's complement representation of -35 in 8

bits?

A) 11011101₂

B) 00100011₂

C) 11011100₂

D) 00100100₂

Answer: A) 11011101₂

Rationale: 35 in binary = 00100011₂. Invert: 11011100₂. Add 1: 11011101₂.




4. The Boolean expression for a NAND gate is:

A) F = A · B

B) F = A + B

C) F = (A · B)'

D) F = (A + B)'

Answer: C) F = (A · B)'

,Rationale: NAND (NOT AND) outputs the inverse of the AND

operation.




5. Which logic gate is equivalent to a NOT gate followed by an AND gate?

A) NAND

B) NOR

C) XOR

D) XNOR

Answer: A) NAND

Rationale: NAND = NOT (AND). A NAND gate is equivalent to an AND

gate with an inverted output.




6. Simplify the Boolean expression: F = A·B + A·B' + A'·B

A) A + B

B) A·B

C) A ⊕ B

D) A + B'

Answer: A) A + B

, Rationale: A·B + A·B' = A(B + B') = A. Then A + A'·B = A + B.




7. A 4-to-1 multiplexer has how many select lines?

A) 1

B) 2

C) 3

D) 4

Answer: B) 2

Rationale: A multiplexer with 2ⁿ inputs requires n select lines. For 4

inputs, n = 2.




8. Which of the following is a characteristic of a D flip-flop?

A) Output toggles on each clock edge

B) Output follows the input when clock is high

C) Output is set to the input value on the clock edge

D) Output is the complement of the input

Answer: C) Output is set to the input value on the clock edge