WGU D402 FINAL TEST 2026 QUESTIONS
WITH CORRECT ANSWERS GRADED A+
◍ Secondary memory.
Answer: Nonvolatile memory used to store programs and data between runs;
typically consists of flash memory in PMDs and magnetic disks in servers.
◍ LEGv8.
Answer: assembly instructions
◍ Reorder Buffer.
Answer: The buffer that holds results in a dynamically scheduled processor
until it is safe to store the results to memory or a register.
◍ L2 cache.
Answer: A cache for main memoryIt is faster than memory, but tends to be
larger and slower than the L1 cache
◍ Protection.
Answer: A set of mechanisms for ensuring that multiple processes sharing
the processor, memory or I/O devices cannot interfere, intentionally or
unintentionally, with one another by reading or writing each other's data.
These mechanism also isolate the operating system from a user process.
◍ ALUOp.
Answer: the 4-bit ALU control input using a small control unit that has as
inputs the opcode field of the instruction and a 2-bit control fieldindicates
whether the operation to be performed should be add (00) for loads and
stores, pass input b (01) for CBZ, or be determined by the operation encoded
in the opcode field (10)10 is ORR, AND, SUB, ADD (R-type)00 is LDUR,
STUR01 is CBZ
◍ Consistency.
, Answer: ensure that writes to a location by different processors are seen in
the same order by all processors. It is defines when written values will be
returned by a read
◍ machine language.
Answer: The language made up of binary-coded instructions that is used
directly by the computer
◍ LDUR.
Answer: load register
◍ B.EQ.
Answer: equal
◍ multiprocessor architecture.
Answer: A unified graphics and computing multiprocessor executes vertex,
geometry, and pixel fragment shader programs, and parallel computing
programsadvantages:Increased throughputCost savingIncreased reliability
◍ throughput.
Answer: the amount of work performed by a system during a given period of
time
◍ Nonvolatile Memory.
Answer: A form of memory that retains data even in the absence of a power
source and that is used to store programs between runs. A DVD disk is
nonvolatile.
◍ Branch prediction.
Answer: A method of resolving a branch hazard that assumes a given
outcome for the branch and proceeds from that assumption rather than
waiting to ascertain the actual outcome.
◍ double precision.
Answer: A floating-point value represented in 64-bit words.
◍ Caller.
Answer: The program that instigates a procedure and provides the necessary
, parameter values.
◍ B.GT.
Answer: greater than
◍ Uniform Memory Access (UMA).
Answer: A multiprocessor in which latency to any word in main memory is
about the same no matter which processor requests the access.
◍ Imprecise interupt.
Answer: The unpopularity of imprecise interrupts led to the standard of
commit units in dynamically scheduled pipelined processors
◍ Exception Syndrome Register (ESR).
Answer: record the cause of the exception
◍ Write serialization.
Answer: Method that ensures writes to a location are seen in the same order
by all processors.Maintaining the order of writes to a given location ensures
that all processors sharing memory read the correct data.
◍ STUR.
Answer: store register
◍ underflow (floating point).
Answer: A situation in which a negative exponent becomes too large to fit in
the exponent field.
◍ Least Recently Used (LRU).
Answer: A replacement scheme in which the block replaced is the one that
has been unused for the longest time.
◍ snooping.
Answer: a popular cache coherence protocol.Each cache contains a copy of
data from a block of physical memory along with a copy of the sharing
status of that block. Each cache contains a controller that monitors, or
snoops, activity on a shared communication medium to determine if any
action is needed to ensure cache coherence.
WITH CORRECT ANSWERS GRADED A+
◍ Secondary memory.
Answer: Nonvolatile memory used to store programs and data between runs;
typically consists of flash memory in PMDs and magnetic disks in servers.
◍ LEGv8.
Answer: assembly instructions
◍ Reorder Buffer.
Answer: The buffer that holds results in a dynamically scheduled processor
until it is safe to store the results to memory or a register.
◍ L2 cache.
Answer: A cache for main memoryIt is faster than memory, but tends to be
larger and slower than the L1 cache
◍ Protection.
Answer: A set of mechanisms for ensuring that multiple processes sharing
the processor, memory or I/O devices cannot interfere, intentionally or
unintentionally, with one another by reading or writing each other's data.
These mechanism also isolate the operating system from a user process.
◍ ALUOp.
Answer: the 4-bit ALU control input using a small control unit that has as
inputs the opcode field of the instruction and a 2-bit control fieldindicates
whether the operation to be performed should be add (00) for loads and
stores, pass input b (01) for CBZ, or be determined by the operation encoded
in the opcode field (10)10 is ORR, AND, SUB, ADD (R-type)00 is LDUR,
STUR01 is CBZ
◍ Consistency.
, Answer: ensure that writes to a location by different processors are seen in
the same order by all processors. It is defines when written values will be
returned by a read
◍ machine language.
Answer: The language made up of binary-coded instructions that is used
directly by the computer
◍ LDUR.
Answer: load register
◍ B.EQ.
Answer: equal
◍ multiprocessor architecture.
Answer: A unified graphics and computing multiprocessor executes vertex,
geometry, and pixel fragment shader programs, and parallel computing
programsadvantages:Increased throughputCost savingIncreased reliability
◍ throughput.
Answer: the amount of work performed by a system during a given period of
time
◍ Nonvolatile Memory.
Answer: A form of memory that retains data even in the absence of a power
source and that is used to store programs between runs. A DVD disk is
nonvolatile.
◍ Branch prediction.
Answer: A method of resolving a branch hazard that assumes a given
outcome for the branch and proceeds from that assumption rather than
waiting to ascertain the actual outcome.
◍ double precision.
Answer: A floating-point value represented in 64-bit words.
◍ Caller.
Answer: The program that instigates a procedure and provides the necessary
, parameter values.
◍ B.GT.
Answer: greater than
◍ Uniform Memory Access (UMA).
Answer: A multiprocessor in which latency to any word in main memory is
about the same no matter which processor requests the access.
◍ Imprecise interupt.
Answer: The unpopularity of imprecise interrupts led to the standard of
commit units in dynamically scheduled pipelined processors
◍ Exception Syndrome Register (ESR).
Answer: record the cause of the exception
◍ Write serialization.
Answer: Method that ensures writes to a location are seen in the same order
by all processors.Maintaining the order of writes to a given location ensures
that all processors sharing memory read the correct data.
◍ STUR.
Answer: store register
◍ underflow (floating point).
Answer: A situation in which a negative exponent becomes too large to fit in
the exponent field.
◍ Least Recently Used (LRU).
Answer: A replacement scheme in which the block replaced is the one that
has been unused for the longest time.
◍ snooping.
Answer: a popular cache coherence protocol.Each cache contains a copy of
data from a block of physical memory along with a copy of the sharing
status of that block. Each cache contains a controller that monitors, or
snoops, activity on a shared communication medium to determine if any
action is needed to ensure cache coherence.
