WGU D560 FINAL TEST 2026 QUESTIONS
WITH CORRECT ANSWERS GRADED A+
◍ base address.
Answer: starting address of an array in memory (5000 below)
◍ RAID 0 (Disk Striping).
Answer: Disk Striping. Disk striping requires at least two drives. It does not
provide redundancy to data. If any one drive fails, all data is lost.
◍ Uniform Memory Access (UMA).
Answer: A multiprocessor in which latency to any word in main memory is
about the same no matter which processor requests the access.
◍ Memory hierarchy.
Answer: A structure that uses multiple levels of memories; as the distance
from the processor increases, the size of the memories and the access time
both increase.
◍ Return address.
Answer: A link to the calling site that allows a procedure to return to the
proper address; in MIPS it is stored in registerLR (X30)
◍ FCMPS, FCMPD.
Answer: Single- and double-precision comparison
◍ wafer.
Answer: A slice from a silicon ingot no more than 0.1 inches thick, used to
create chips.
◍ Dynamic Random Access Memory (DRAM).
Answer: Memory built as an integrated circuit; it provides random access to
any location. Access times are 50 nanoseconds and cost per gigabyte in
2012 was $5 to $10.Multiple DRAMs are used together to contain the
, instructions and data of a program. In contrast to sequential access
memories, such as magnetic tapes, the RAM portion of the term DRAM
means that memory accesses take basically the same amount of time no
matter what portion of the memory is read.Modern DRAMS consist of rows
in each bank
◍ store register.
Answer: instruction complementary to load. It copies data from register to
memory.the format is similar to load; name of the operation, followed by the
register to be stored, then the base register, and finally the offset to select the
array element.
◍ CPU Time Formula.
Answer: (Instructions) x (CPI) x (Clock Cycle Time)
◍ address translation (address mapping).
Answer: the process by which a virtual address is mapped to an address used
to access memory
◍ Streaming processor (SP).
Answer: the primary thread instruction processor in the multiprocessor
◍ very large-scale integrated (VLSI) circuit.
Answer: A device containing hundreds of thousands to millions of
transistors.
◍ forwarding (bypassing).
Answer: A method of resolving a data hazard by retrieving the missing data
element from internal buffers rather than waiting for it to arrive from
programmer-visible registers or memory
◍ L1 cache (primary cache).
Answer: a cache for a cache
◍ LEGv8 LDUR.
Answer: The sum of the constant portion of the instruction and the contents
of the second register forms the memory addressThe U in LDUR stands for
, unscaled immeditate
◍ multimedia extensions (MMX).
Answer: An expanded set of instructions supported by a processor that
provides multimedia-specific functions.
◍ page fault.
Answer: a virtual memory miss
◍ Datapath.
Answer: The component of the processor that performs arithmetic
operations
◍ IBM 360/91.
Answer: Introduced many new concepts, including dynamic detection of
memory hazards, generalized forwarding, and reservation stations.
Tomasulo's algorithmThe internal organization of the 360/91 shares many
features with the Pentium III and Pentium 4, as well as with several other
microprocessors. One major difference was that there was no branch
prediction in the 360/91 and hence no speculation. Another major difference
was that there was no commit unit, so once the instructions finished
execution, they updated the registers.
◍ five-stage pipeline.
Answer: five instructions will be in execution during any single clock
cycle1. IF - instruction fetch2. ID - instruction decode and register file
read3. EX - execution or address calculation4. MEM - data memory
access5. WB - write back
◍ LEGv8 fields.
Answer: 1. opcode - 11 bits - basic operation of the instruction2. rm - 5 bits -
the second register source operand3. shamt - 6 bits - shift amount4. rn - 5
bits - the first register source operand5. rd - 5 bits - the register destination
operand
◍ Single Program, Multiple Data Streams (SPMD).
Answer: The conventional MIMD programming model, where a single
WITH CORRECT ANSWERS GRADED A+
◍ base address.
Answer: starting address of an array in memory (5000 below)
◍ RAID 0 (Disk Striping).
Answer: Disk Striping. Disk striping requires at least two drives. It does not
provide redundancy to data. If any one drive fails, all data is lost.
◍ Uniform Memory Access (UMA).
Answer: A multiprocessor in which latency to any word in main memory is
about the same no matter which processor requests the access.
◍ Memory hierarchy.
Answer: A structure that uses multiple levels of memories; as the distance
from the processor increases, the size of the memories and the access time
both increase.
◍ Return address.
Answer: A link to the calling site that allows a procedure to return to the
proper address; in MIPS it is stored in registerLR (X30)
◍ FCMPS, FCMPD.
Answer: Single- and double-precision comparison
◍ wafer.
Answer: A slice from a silicon ingot no more than 0.1 inches thick, used to
create chips.
◍ Dynamic Random Access Memory (DRAM).
Answer: Memory built as an integrated circuit; it provides random access to
any location. Access times are 50 nanoseconds and cost per gigabyte in
2012 was $5 to $10.Multiple DRAMs are used together to contain the
, instructions and data of a program. In contrast to sequential access
memories, such as magnetic tapes, the RAM portion of the term DRAM
means that memory accesses take basically the same amount of time no
matter what portion of the memory is read.Modern DRAMS consist of rows
in each bank
◍ store register.
Answer: instruction complementary to load. It copies data from register to
memory.the format is similar to load; name of the operation, followed by the
register to be stored, then the base register, and finally the offset to select the
array element.
◍ CPU Time Formula.
Answer: (Instructions) x (CPI) x (Clock Cycle Time)
◍ address translation (address mapping).
Answer: the process by which a virtual address is mapped to an address used
to access memory
◍ Streaming processor (SP).
Answer: the primary thread instruction processor in the multiprocessor
◍ very large-scale integrated (VLSI) circuit.
Answer: A device containing hundreds of thousands to millions of
transistors.
◍ forwarding (bypassing).
Answer: A method of resolving a data hazard by retrieving the missing data
element from internal buffers rather than waiting for it to arrive from
programmer-visible registers or memory
◍ L1 cache (primary cache).
Answer: a cache for a cache
◍ LEGv8 LDUR.
Answer: The sum of the constant portion of the instruction and the contents
of the second register forms the memory addressThe U in LDUR stands for
, unscaled immeditate
◍ multimedia extensions (MMX).
Answer: An expanded set of instructions supported by a processor that
provides multimedia-specific functions.
◍ page fault.
Answer: a virtual memory miss
◍ Datapath.
Answer: The component of the processor that performs arithmetic
operations
◍ IBM 360/91.
Answer: Introduced many new concepts, including dynamic detection of
memory hazards, generalized forwarding, and reservation stations.
Tomasulo's algorithmThe internal organization of the 360/91 shares many
features with the Pentium III and Pentium 4, as well as with several other
microprocessors. One major difference was that there was no branch
prediction in the 360/91 and hence no speculation. Another major difference
was that there was no commit unit, so once the instructions finished
execution, they updated the registers.
◍ five-stage pipeline.
Answer: five instructions will be in execution during any single clock
cycle1. IF - instruction fetch2. ID - instruction decode and register file
read3. EX - execution or address calculation4. MEM - data memory
access5. WB - write back
◍ LEGv8 fields.
Answer: 1. opcode - 11 bits - basic operation of the instruction2. rm - 5 bits -
the second register source operand3. shamt - 6 bits - shift amount4. rn - 5
bits - the first register source operand5. rd - 5 bits - the register destination
operand
◍ Single Program, Multiple Data Streams (SPMD).
Answer: The conventional MIMD programming model, where a single
