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WGU C952 – Computer Architecture EXAM QUESTIONS AND
CORRECT VERIFIED SOLUTIONS LATEST UPDATE THIS YEAR –
JUST RELEASED
WGU C952 – Computer Architecture: Exam Coverage (Brief)
The exam assesses understanding of computer architecture concepts, including:
• Digital Logic Fundamentals – gates, flip-flops, combinational/sequential circuits
• Processor Architecture – CPU components, ALU, control unit, pipelining
• Memory Hierarchy – cache, RAM, registers, virtual memory
• Instruction Set Architecture (ISA) – types, addressing modes, instruction formats
• Data Representation – binary, hexadecimal, two’s complement, floating point
• Input/Output Systems – buses, I/O methods, interrupts, DMA
• Performance Metrics – clock speed, CPI, MIPS, throughput, speedup calculations
• Assembly Language Concepts – simple instruction sequences, branching, loops
• Computer System Organization – Von Neumann vs. Harvard architecture, system buses
• Pipeline and Parallelism – hazards, forwarding, multi-core concepts
MCQs with Rationales – Questions 1–100
1. Which of the following best describes the function of the ALU in a CPU?
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A. Stores instructions and data temporarily
B. Performs arithmetic and logical operations on data
C. Manages memory access and paging
D. Controls the timing of the system bus
Answer: B
Rationale: The Arithmetic Logic Unit (ALU) performs all arithmetic and logical operations, such
as addition, subtraction, AND, OR, and comparisons.
2. In a computer using a 32-bit two’s complement system, what is the decimal value of
11111111 11111111 11111111 11110100?
A. -12
B. -8
C. 244
D. 12
Answer: A
Rationale: Two’s complement negative numbers are calculated by inverting bits and adding 1.
11111111 11111111 11111111 11110100 = -12 in decimal.
3. Which memory type is fastest and located closest to the CPU?
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A. RAM
B. Hard Disk
C. Cache
D. SSD
Answer: C
Rationale: Cache memory is closest to the CPU, providing the fastest access to frequently used
data.
4. In a pipelined CPU, a data hazard occurs when:
A. Two instructions require the same memory location
B. An instruction depends on the result of a previous instruction not yet completed
C. Branch prediction fails
D. Cache miss occurs
Answer: B
Rationale: A data hazard arises when an instruction needs data that is still being computed in
an earlier pipeline stage.
5. Which addressing mode uses a constant value embedded in the instruction?
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A. Immediate addressing
B. Direct addressing
C. Register addressing
D. Indirect addressing
Answer: A
Rationale: Immediate addressing uses a literal constant as the operand in the instruction itself.
6. What is the main difference between Harvard and Von Neumann architectures?
A. Harvard uses parallel buses for instructions and data, Von Neumann uses a single bus
B. Von Neumann cannot execute instructions
C. Harvard only supports pipelining
D. Von Neumann has no memory
Answer: A
Rationale: Harvard architecture separates instruction and data memory with different buses,
while Von Neumann uses one shared memory bus.
7. Which of the following best describes an instruction set architecture (ISA)?
A. The physical layout of the CPU components
B. The set of machine-level commands the CPU can execute
WGU C952 – Computer Architecture EXAM QUESTIONS AND
CORRECT VERIFIED SOLUTIONS LATEST UPDATE THIS YEAR –
JUST RELEASED
WGU C952 – Computer Architecture: Exam Coverage (Brief)
The exam assesses understanding of computer architecture concepts, including:
• Digital Logic Fundamentals – gates, flip-flops, combinational/sequential circuits
• Processor Architecture – CPU components, ALU, control unit, pipelining
• Memory Hierarchy – cache, RAM, registers, virtual memory
• Instruction Set Architecture (ISA) – types, addressing modes, instruction formats
• Data Representation – binary, hexadecimal, two’s complement, floating point
• Input/Output Systems – buses, I/O methods, interrupts, DMA
• Performance Metrics – clock speed, CPI, MIPS, throughput, speedup calculations
• Assembly Language Concepts – simple instruction sequences, branching, loops
• Computer System Organization – Von Neumann vs. Harvard architecture, system buses
• Pipeline and Parallelism – hazards, forwarding, multi-core concepts
MCQs with Rationales – Questions 1–100
1. Which of the following best describes the function of the ALU in a CPU?
, Page 2 of 98
A. Stores instructions and data temporarily
B. Performs arithmetic and logical operations on data
C. Manages memory access and paging
D. Controls the timing of the system bus
Answer: B
Rationale: The Arithmetic Logic Unit (ALU) performs all arithmetic and logical operations, such
as addition, subtraction, AND, OR, and comparisons.
2. In a computer using a 32-bit two’s complement system, what is the decimal value of
11111111 11111111 11111111 11110100?
A. -12
B. -8
C. 244
D. 12
Answer: A
Rationale: Two’s complement negative numbers are calculated by inverting bits and adding 1.
11111111 11111111 11111111 11110100 = -12 in decimal.
3. Which memory type is fastest and located closest to the CPU?
, Page 3 of 98
A. RAM
B. Hard Disk
C. Cache
D. SSD
Answer: C
Rationale: Cache memory is closest to the CPU, providing the fastest access to frequently used
data.
4. In a pipelined CPU, a data hazard occurs when:
A. Two instructions require the same memory location
B. An instruction depends on the result of a previous instruction not yet completed
C. Branch prediction fails
D. Cache miss occurs
Answer: B
Rationale: A data hazard arises when an instruction needs data that is still being computed in
an earlier pipeline stage.
5. Which addressing mode uses a constant value embedded in the instruction?
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A. Immediate addressing
B. Direct addressing
C. Register addressing
D. Indirect addressing
Answer: A
Rationale: Immediate addressing uses a literal constant as the operand in the instruction itself.
6. What is the main difference between Harvard and Von Neumann architectures?
A. Harvard uses parallel buses for instructions and data, Von Neumann uses a single bus
B. Von Neumann cannot execute instructions
C. Harvard only supports pipelining
D. Von Neumann has no memory
Answer: A
Rationale: Harvard architecture separates instruction and data memory with different buses,
while Von Neumann uses one shared memory bus.
7. Which of the following best describes an instruction set architecture (ISA)?
A. The physical layout of the CPU components
B. The set of machine-level commands the CPU can execute
