ECE 331 MODULE 9 SERIAL COMMUNICATION EXAM QUESTIONS ANSWERED CORRECTLY LATEST
UPDATE 2026
Standard digital communication interfaces - Answers -establish the function and protocol of signals
used to exchange data between two (or more) digital components in a system
-Function: data, clock, "handshaking"
-Protocol: relative timing characteristics of signals in a standard interface
Two primary types of digital communications - Answers -parallel (multiple data lines, generally one
byte worth, and multiple data values transmitted simultaneously)
-serial (single data line, bits sent in series, one bit at a time, sequentially)
bit rate - Answers bits per second
bit cell - Answers time to transmit a single bit
BAUD rate - Answers -bits per second
-baudrate=1/bit-time
Synchronous - Answers data bits read at clock edge
Asynchonous - Answers no clock, data read at preset interval
Separate - Answers -Data can be transmitted and received simultaneously
-similar to full duplex
-for hardwired communication, requires multiple data lines
Shared - Answers -Data either incoming or outgoing (not both) at any given time
-similar to half duplex
-for hardwired communication, requires only one data line
UART - Answers -Universal asynchronous receiver/transmitter
-Serially transmit/receive a byte (5-8 bits) of data written/stored to a register
-includes a single (start) bit prefix and a 1 or 2 (stop) bit suffix (lease significant bit sent first)
-RS-232
-asynchronous (no clock signal, data read at predetermined BAUD rate, BAUD rate must match on
both sides of the interface, typically use start/stop bits to mark bytes)
RS-232 - Answers -PC serial port
-specific UART "standard"
Standard - Answers defined voltage and timing characteristics
UART Signals - Answers Transmit Data (TxD)
Receive Data (RxD)
Signal Ground (SG)
Full duplex (separate rreceive & transmit lines)
bandwidth (+eqn) - Answers -data per unit time
-bandwidth=(data-bits/frame-bits)*baudrate
Tx Operation - Answers -Data written to UART0_DR_R
-passes through 16-element FIFO
-permits small amount of data rate matching between processor and UART
-Shift clock is generated from 16x clock (permits differences in Tx and Rx clocks to be reconciled)
Rx Operation: RXFE - Answers is 0 when data are available
Rx Operation: RXFF - Answers Is 1 when FIFO is full
Rx Operation: OE - Answers -FIFO entry
-set when FIFO is full and a new frame has arrived
Rx Operation: BE - Answers -FIFO entry
-set when Tx signal held low for more than one frame(break)
Rx Operation: PE - Answers -FIFO entry
-Set if frame parity error
Rx Operation: FE - Answers -FIFO entry
-set if stop bit timing error
SSI - Answers -Synchronous Serial Interface
-synchronous serial data link standard (originally introduces by Motorola as Serial Peripheral Interface
(SPI)
-operates in full duplex mode using separate in/out data signals
-devices communicate in master/slave mode
-multiple slave devices are allowed with individual Slave Select lines
UPDATE 2026
Standard digital communication interfaces - Answers -establish the function and protocol of signals
used to exchange data between two (or more) digital components in a system
-Function: data, clock, "handshaking"
-Protocol: relative timing characteristics of signals in a standard interface
Two primary types of digital communications - Answers -parallel (multiple data lines, generally one
byte worth, and multiple data values transmitted simultaneously)
-serial (single data line, bits sent in series, one bit at a time, sequentially)
bit rate - Answers bits per second
bit cell - Answers time to transmit a single bit
BAUD rate - Answers -bits per second
-baudrate=1/bit-time
Synchronous - Answers data bits read at clock edge
Asynchonous - Answers no clock, data read at preset interval
Separate - Answers -Data can be transmitted and received simultaneously
-similar to full duplex
-for hardwired communication, requires multiple data lines
Shared - Answers -Data either incoming or outgoing (not both) at any given time
-similar to half duplex
-for hardwired communication, requires only one data line
UART - Answers -Universal asynchronous receiver/transmitter
-Serially transmit/receive a byte (5-8 bits) of data written/stored to a register
-includes a single (start) bit prefix and a 1 or 2 (stop) bit suffix (lease significant bit sent first)
-RS-232
-asynchronous (no clock signal, data read at predetermined BAUD rate, BAUD rate must match on
both sides of the interface, typically use start/stop bits to mark bytes)
RS-232 - Answers -PC serial port
-specific UART "standard"
Standard - Answers defined voltage and timing characteristics
UART Signals - Answers Transmit Data (TxD)
Receive Data (RxD)
Signal Ground (SG)
Full duplex (separate rreceive & transmit lines)
bandwidth (+eqn) - Answers -data per unit time
-bandwidth=(data-bits/frame-bits)*baudrate
Tx Operation - Answers -Data written to UART0_DR_R
-passes through 16-element FIFO
-permits small amount of data rate matching between processor and UART
-Shift clock is generated from 16x clock (permits differences in Tx and Rx clocks to be reconciled)
Rx Operation: RXFE - Answers is 0 when data are available
Rx Operation: RXFF - Answers Is 1 when FIFO is full
Rx Operation: OE - Answers -FIFO entry
-set when FIFO is full and a new frame has arrived
Rx Operation: BE - Answers -FIFO entry
-set when Tx signal held low for more than one frame(break)
Rx Operation: PE - Answers -FIFO entry
-Set if frame parity error
Rx Operation: FE - Answers -FIFO entry
-set if stop bit timing error
SSI - Answers -Synchronous Serial Interface
-synchronous serial data link standard (originally introduces by Motorola as Serial Peripheral Interface
(SPI)
-operates in full duplex mode using separate in/out data signals
-devices communicate in master/slave mode
-multiple slave devices are allowed with individual Slave Select lines
