ECEN 350 Final Study Questions With
Correct Answers
(True |or |False) |The |following |is |the |complete |RTL |description |of |the |"AND" |instruction:
R[rd] |= |R[rs] |& |R[rt];
False
Adding |two |ports |to |an |SRAM |means |increasing |each |cell |by |_____ |transistors. |(how |many?)
4
Fetch, |_______ |and |Execute |are |the |three |phases |of |an |instructions |life-cycle.
decode
For |all |D-Type |instructions, |Read |Data |2 |is |connected |to |the |ALU.
False
Hardware |that |is |not |in |use |for |a |given |instruction |(on |the |unified |hardware) |is |removed |until |
needed |to |save |power.
False
,RTL |defines |the |actions |of |an |instruction |in |terms |of |operations |performed |on |registers, |with |
the |outcome |being |placed |in |another |register.
True
RTL |stands |for |______________________.
register |transfer |language
The |B |instruction |does |not |require |the |registerfile |at |all.
True
The |fastest |path |through |the |logic |determines |its |critical |path |and |hence |its |clock |frequency.
False
The |register |file |must |have |three |ports |(two |read |and |one |write) |in |order |to |directly |support |
D-Type |instructions.
False
There |are |many |different |possible |implementations |of |a |particular |ISA |in |hardware.
True
, _______ |are |used |to |allow |for |different |inputs |to |a |given |piece |of |hardware |when |it |requires |
different |inputs |when |used |by |different |instructions. |For |example, |it |is |used |on |the |input |to |
the |registerfile's |Write |Address |input |to |select |between |Rd |and |Rt |depending |on |which |
instruction |is |executing.
multiplexers
For |all |R-Type |instruction, |Read |Data |2 |is |connected |to |the |ALU.
True
In |the |LDUR |and |STUR |instructions, |the |ALU |is |used |for |effective |__________ |calculation.
address
The |registerfile |does |not |produce |any |output |on |Read |Data |1 |and |Read |Data |2 |for |the |B |
instruction.
False
Assuming |Fetch |has |placed |an |instruction |on |the |bus |called |I[31:0] |(in |Verilog |notation), |which
|wires |should |be |connected |to |"Read |Addr |2" |on |the |register |file |for |the |proper |execution |of |
R-Type |instructions.
I[20:16]
For |the |CBZ |instruction, |the |ALU |must |be |set |to |perform |the |"pass |_________" |operation.
Correct Answers
(True |or |False) |The |following |is |the |complete |RTL |description |of |the |"AND" |instruction:
R[rd] |= |R[rs] |& |R[rt];
False
Adding |two |ports |to |an |SRAM |means |increasing |each |cell |by |_____ |transistors. |(how |many?)
4
Fetch, |_______ |and |Execute |are |the |three |phases |of |an |instructions |life-cycle.
decode
For |all |D-Type |instructions, |Read |Data |2 |is |connected |to |the |ALU.
False
Hardware |that |is |not |in |use |for |a |given |instruction |(on |the |unified |hardware) |is |removed |until |
needed |to |save |power.
False
,RTL |defines |the |actions |of |an |instruction |in |terms |of |operations |performed |on |registers, |with |
the |outcome |being |placed |in |another |register.
True
RTL |stands |for |______________________.
register |transfer |language
The |B |instruction |does |not |require |the |registerfile |at |all.
True
The |fastest |path |through |the |logic |determines |its |critical |path |and |hence |its |clock |frequency.
False
The |register |file |must |have |three |ports |(two |read |and |one |write) |in |order |to |directly |support |
D-Type |instructions.
False
There |are |many |different |possible |implementations |of |a |particular |ISA |in |hardware.
True
, _______ |are |used |to |allow |for |different |inputs |to |a |given |piece |of |hardware |when |it |requires |
different |inputs |when |used |by |different |instructions. |For |example, |it |is |used |on |the |input |to |
the |registerfile's |Write |Address |input |to |select |between |Rd |and |Rt |depending |on |which |
instruction |is |executing.
multiplexers
For |all |R-Type |instruction, |Read |Data |2 |is |connected |to |the |ALU.
True
In |the |LDUR |and |STUR |instructions, |the |ALU |is |used |for |effective |__________ |calculation.
address
The |registerfile |does |not |produce |any |output |on |Read |Data |1 |and |Read |Data |2 |for |the |B |
instruction.
False
Assuming |Fetch |has |placed |an |instruction |on |the |bus |called |I[31:0] |(in |Verilog |notation), |which
|wires |should |be |connected |to |"Read |Addr |2" |on |the |register |file |for |the |proper |execution |of |
R-Type |instructions.
I[20:16]
For |the |CBZ |instruction, |the |ALU |must |be |set |to |perform |the |"pass |_________" |operation.
