Spring 2026: CS/ECE 3810 Computer Organization | CS / ECE 3810 Final Exam | Complete 100% Solutions.

Spring 2026: CS/ECE 3810 Computer Organization | CS / ECE 3810 Final Exam | Complete 100% Solutions. Name: UID: CS / ECE 3810 Final Exam Notes: Students are allowed to bring 3 A4/letter-sized sheets of paper with anything written/printed on both sides. In addition, you may bring the “green sheet”. No phones, laptops, or internet access are allowed. You may bring a simple calculator with no internet connectivity, that can be used for any numeric calculations (but it’s also ok to write a mathematical term, say 1.4/2.2 GHz without doing the calculation). You may of course not use your phone to surf the web or consult with others during the test. You may also not use the MARS simulator or other calculators/tools for numeric conversions. If necessary, make reasonable assumptions and clearly state them. The only clarifications you may ask for during the exam are definitions of terms. You will receive partial credit if you show your steps and explain your line of thinking, so attempt every question even if you can’t fully solve it. Complete your answers in the space provided (including the back side of each page). Turn in your answer sheets before 12:30pm. The test is worth 100 points and you have about 120 minutes, so allocate time accordingly. Confirm that you have 12 questions on 11 pages. 1. Represent the decimal number 19.875 in IEEE 754 single-precision format. (6 points) 12. (a) A 2 MB L2 cache has a 64 byte block size and is 8-way set-associative. How many sets does the cache have? How many bits are used for the offset, index, and tag, assuming that the CPU provides 32-bit addresses? How large is the tag array? If you do not explain your steps/equations, you will not receive partial credit for an incorrect answer. (6 points) (b) The processor issues a request for byte address 144 (decimal representation 144). For the cache described above, what are the equations used to compute the index, offset, and tag bits for this address? For the cache described above, what are the index, offset, and tag for this address (feel free to use binary or decimal representations)? (6 points) 23. Consider the high level source code below dealing with integers i, j, and an array of integers a[...]: if (a[i] == j) { a[i] = 2j; } else { a[i] = 4j; } i = i + 1; Produce the MIPS assembly code for the above sequence. You can assume that $s0 already has the address of a[0], $s1 has the value of i, $s2 has the value of j. Add comments to your code for clarity. (10 points) 34. Consider an in-order pipeline that has the following stages. A register read takes an entire cycle and a register write takes an entire cycle. Fetch: Decode: Regread: IntALU: Regwrite : IntALU: Datamem: Datamem: Datamem: Regwrite After instruction fetch, the instruction goes through a separate Decode stage where dependences are analyzed, then a separate Regread stage where input operands are read from the register file. After this, an instruction takes one of two possible paths. Int-adds go through the stages labeled “IntALU” and “Regwrite”. Loads/stores go through the stages labeled “IntALU”, “Datamem”, “Datamem”, “Datamem”, and “Regwrite”, i.e., it takes three cycles to retrieve data from the data memory unit. How many stall cycles are introduced between the following pairs of successive instructions (i) for a processor with no register bypassing and (ii) for a processor with full bypassing? Draw appropriate pipeline diagrams and indicate the points of production/consumption to show how you arrived at your answer. (8 points) (a) add $1, $2, $3 add $4, $1, $2 STALLS WITHOUT BYPASSING: STALLS WITH BYPASSING: (b) lw $1, 8($2) sw $1, 0($3) STALLS WITHOUT BYPASSING: STALLS WITH BYPASSING: 45. Consider a 3-processor multiprocessor connected with a shared bus that has the following properties: (i) centralized shared memory accessible with the bus, (ii) snooping-based MSI cache coherence protocol, (iii) write-invalidate policy. Also assume that the caches have a writeback policy. Initially, the caches all have invalid data. The processors issue the following four requests, one after the other. Similar to the lecture slides, fill in the following table to indicate what happens for every request. Also indicate if/when memory writeback is performed. (8 points) (a) P1: Write X (b) P2: Write X (c) P1: Read X (d) P1: Write X Request Cache Request on bus Who responds State State State Hit/Miss Cache 1 Cache 2 Cache 3 Inv Inv Inv P1: Wr X P2: Wr X P1: Rd X P1: Wr X 56. Consider a MIPS procedure procA that calls another procedure procB. (a) What MIPS instruction is used to implement the procedure call? (2 points) (b) What MIPS instruction is used to return from procB to procA? (2 points) (c) Assume that procB uses registers $t1, $t2, $s1. The code in procB starts by saving relevant register values on the stack. Write the code to grow the stack and save these relevant values on the stack, while following the MIPS guidelines for caller-saved and callee-saved registers. (4 points) 67. Design a finite state machine that controls the sprinkler system at an apple orchard. The sprinklers are turned on from 5am-6am every day, with a few exceptions: (i) If a rain detector sensor has detected rain in the past 12 hours, the sprinklers are not turned on. (ii) The sprinklers are never turned on for three consecutive days. (8 points) (a) What are the states for the finite state machine controlling the sprinkler system? (b) What are the inputs to the circuit and what values can those inputs have? (c) Draw the finite state diagram for this circuit. 78. An Intel processor at 2 GHz (Normal mode) consumes 80 W of power, of which 60 W is dynamic power and 20 W is leakage power. A program takes 10 seconds to run on this processor in Normal mode, and it is entirely CPU-bound. When the processor enters Turbo-boost mode, its frequency is increased to 4 GHz. How much energy does the program consume when running in Normal and Turbo-boost modes? (6 points) 9. When designing a processor, is there a performance-optimal pipeline depth one should strive for? Explain. (4 points) 810. When using the IEEE 754 standard, what is the difference between 2.0 and the smallest 32-bit floating point value that is greater than 2.0? (6 points) 11. Consider a program that can execute with no stalls and a CPI of 1 if the underlying processor can somehow magically service every load instruction with a 1-cycle L1 cache hit. In practice, 10% of all load instructions suffer from an L1 cache miss, 3% of all load instructions suffer from an L2 cache miss, and 1% of all load instructions suffer from an L3 cache miss (and are serviced by the memory system). An L1 cache miss stalls the processor for 10 cycles while the L2 is looked up. An L2 cache miss stalls the processor for 20 cycles while the L3 is looked up. An L3 cache miss stalls the processor for an additional 100 cycles while data is fetched from memory. What is the CPI for this program if 20% of the program’s instructions are load instructions? (6 points) 912. (a) In the out-of-order processor design, why did we introduce additional temporary registers in the reorder buffer? (3 points) (b) When translating a virtual address to a physical address, a hardware structure in the processor is first examined. If the translation is not found in this hardware structure, a larger structure in memory is examined. What are the names of these two structures? (2 points) (c) What is the 2-instruction sequence in a program that can convert a program secret into a cache footprint that may be visible to attackers? (3 points) (d) In a RAID-3 system, assume that a byte is spread across 8 disks and its parity is stored on a 9th disk. What is the parity bit for each of the following two bytes? How is parity defined? (3 points) i. ii. (e) Why do modern processors not implement the sequential consistency model? (3 points) 10(f) How are lock-unlock primitives useful in shared-memory multi-threaded applications? (2 points) (g) List two GPU hardware features that make it different from a general-purpose CPU. (2 points) 11