ITE 221 Exam 3 Review UPDATED
QUESTIONS AND CORRECT ANSWERS
L1 or level one - CORRECT ANSWER A(n) _____ cache is generally implemented on the
same chip as the CPU.
a. level 1
b. level 3
c. level 2
d. level 4
cache - CORRECT ANSWER A(n) _____ is an area of fast memory where data held in a
storage device is prefetched in anticipation of future requests for the data.
a. RAM
b. Register
c. cache
d. fetcher
cache swap - CORRECT ANSWER A cache controller is a hardware device that initiates a(n)
_____ when it detects a cache miss.
a. cache miss
b. cache swap
c. cache turn
d. cache handler
control bus - CORRECT ANSWER The _____ transmits command, timing, and status signals
between devices in a computer system and carries interrupts, command responses, status codes, and
similar messages.
a. bus clock
b. control bus
c. data bus
d. system bus
,stack pointer - CORRECT ANSWER The _____ is a special-purpose register that always points
to the next empty address in the stack.
a.
b.
c.
d.
machine state - CORRECT ANSWER The set of register values stored in the stack while
processing an interrupt is also called the _____.
interrupt handler - CORRECT ANSWER A(n) _____ is a program stored in a separate part of
primary storage to process a specific interrupt.
stack - CORRECT ANSWER During interrupt processing, register values of a suspended
process are held on the _____.
cache controller - CORRECT ANSWER A(n) _____ is a special-purpose processor dedicated to
managing cache content.
address bus - CORRECT ANSWER The _____ transmits a memory address when primary
storage is the sending or receiving device.
linear address space - CORRECT ANSWER The CPU and bus normally view and storage
device as a(n) _____, ignoring the device's physical storage organization.
logical accesses - CORRECT ANSWER Part of a device controller's function is to translate
_____ into physical accesses.
DMA - CORRECT ANSWER A(n) _____ controller assumes the role of bus master for all
transfers between memory and other storage or I/O devices, leaving the CPU free to execute
computation and data movement instructions.
channel - CORRECT ANSWER A(n) _____ is a high-capacity device controller used in
mainframe computers.
,cache hit - CORRECT ANSWER When a read operation accesses data already contained in the
cache, it's called a(n) _____.
bus protocol - CORRECT ANSWER The _____ defines the format, content, and timing of data,
memory addresses, and control messages sent across the bus.
multicore - CORRECT ANSWER In _____ architecture, multiple CPUs and cache memory are
embedded on a single chip.
scaling up - CORRECT ANSWER The term _____ describes methods of increasing processing
and other computer system power by using larger and more powerful computers.
a. Scaling up
b. Scaling down
c. Scaling out
d. Scaling in
Storage - CORRECT ANSWER Examples of a(n) _____ bus include SATA and SCSI.
TRUE - CORRECT ANSWER The secondary storage devices for a mainframe could include
many different types of storage devices, such as magnetic disks, optical discs, and magnetic tape
drives.
TRUE - CORRECT ANSWER MPEG standards address recording and encoding for both audio
and video data.
TRUE - CORRECT ANSWER The memory bus has a much higher data transfer rate than the
system bus because of its shorter length, higher clock rate, and (in most computers) large number of
parallel communication lines.
read operations - CORRECT ANSWER Most performance benefits of a cache occur during
_____.
, DMA controller - CORRECT ANSWER Under direct memory access, a device called a _____
is attached to the bus and to the main memory.
TRUE - CORRECT ANSWER Zip files and archives are examples of lossless compression.
scaling out - CORRECT ANSWER _____ is an approach that partitions processing and
othertasks among multiple computer systems.
FALSE - CORRECT ANSWER The way in which secondary storage devices are controlled on
a desktop is the same as on a mainframe.
TRUE - CORRECT ANSWER PCIe buses can provide multiple lanes, and the cost increases
with the number of lanes.
TRUE - CORRECT ANSWER Both multicore and multiple-processor architectures are
examples of scaling up because they increase the power of a single computer system.
peripheral devices - CORRECT ANSWER There are typically multiple storage and I/O devices
connected to a computer, collectively referred to as _____.
law of diminishing returns - CORRECT ANSWER The _____ states that when multiple
resources are required to produce something useful, adding more of a single resource produces fewer
benefits.
TRUE - CORRECT ANSWER Devices with low data transfer demand can use a single lane,
and devices with higher requirements can increase their available data transfer rate by using additional
lanes.
TRUE - CORRECT ANSWER Examples of external I/O buses include USB and FireWire.
TRUE - CORRECT ANSWER A system bus connects computer system components, including
the CPU memory, storage, and I/O devices.
QUESTIONS AND CORRECT ANSWERS
L1 or level one - CORRECT ANSWER A(n) _____ cache is generally implemented on the
same chip as the CPU.
a. level 1
b. level 3
c. level 2
d. level 4
cache - CORRECT ANSWER A(n) _____ is an area of fast memory where data held in a
storage device is prefetched in anticipation of future requests for the data.
a. RAM
b. Register
c. cache
d. fetcher
cache swap - CORRECT ANSWER A cache controller is a hardware device that initiates a(n)
_____ when it detects a cache miss.
a. cache miss
b. cache swap
c. cache turn
d. cache handler
control bus - CORRECT ANSWER The _____ transmits command, timing, and status signals
between devices in a computer system and carries interrupts, command responses, status codes, and
similar messages.
a. bus clock
b. control bus
c. data bus
d. system bus
,stack pointer - CORRECT ANSWER The _____ is a special-purpose register that always points
to the next empty address in the stack.
a.
b.
c.
d.
machine state - CORRECT ANSWER The set of register values stored in the stack while
processing an interrupt is also called the _____.
interrupt handler - CORRECT ANSWER A(n) _____ is a program stored in a separate part of
primary storage to process a specific interrupt.
stack - CORRECT ANSWER During interrupt processing, register values of a suspended
process are held on the _____.
cache controller - CORRECT ANSWER A(n) _____ is a special-purpose processor dedicated to
managing cache content.
address bus - CORRECT ANSWER The _____ transmits a memory address when primary
storage is the sending or receiving device.
linear address space - CORRECT ANSWER The CPU and bus normally view and storage
device as a(n) _____, ignoring the device's physical storage organization.
logical accesses - CORRECT ANSWER Part of a device controller's function is to translate
_____ into physical accesses.
DMA - CORRECT ANSWER A(n) _____ controller assumes the role of bus master for all
transfers between memory and other storage or I/O devices, leaving the CPU free to execute
computation and data movement instructions.
channel - CORRECT ANSWER A(n) _____ is a high-capacity device controller used in
mainframe computers.
,cache hit - CORRECT ANSWER When a read operation accesses data already contained in the
cache, it's called a(n) _____.
bus protocol - CORRECT ANSWER The _____ defines the format, content, and timing of data,
memory addresses, and control messages sent across the bus.
multicore - CORRECT ANSWER In _____ architecture, multiple CPUs and cache memory are
embedded on a single chip.
scaling up - CORRECT ANSWER The term _____ describes methods of increasing processing
and other computer system power by using larger and more powerful computers.
a. Scaling up
b. Scaling down
c. Scaling out
d. Scaling in
Storage - CORRECT ANSWER Examples of a(n) _____ bus include SATA and SCSI.
TRUE - CORRECT ANSWER The secondary storage devices for a mainframe could include
many different types of storage devices, such as magnetic disks, optical discs, and magnetic tape
drives.
TRUE - CORRECT ANSWER MPEG standards address recording and encoding for both audio
and video data.
TRUE - CORRECT ANSWER The memory bus has a much higher data transfer rate than the
system bus because of its shorter length, higher clock rate, and (in most computers) large number of
parallel communication lines.
read operations - CORRECT ANSWER Most performance benefits of a cache occur during
_____.
, DMA controller - CORRECT ANSWER Under direct memory access, a device called a _____
is attached to the bus and to the main memory.
TRUE - CORRECT ANSWER Zip files and archives are examples of lossless compression.
scaling out - CORRECT ANSWER _____ is an approach that partitions processing and
othertasks among multiple computer systems.
FALSE - CORRECT ANSWER The way in which secondary storage devices are controlled on
a desktop is the same as on a mainframe.
TRUE - CORRECT ANSWER PCIe buses can provide multiple lanes, and the cost increases
with the number of lanes.
TRUE - CORRECT ANSWER Both multicore and multiple-processor architectures are
examples of scaling up because they increase the power of a single computer system.
peripheral devices - CORRECT ANSWER There are typically multiple storage and I/O devices
connected to a computer, collectively referred to as _____.
law of diminishing returns - CORRECT ANSWER The _____ states that when multiple
resources are required to produce something useful, adding more of a single resource produces fewer
benefits.
TRUE - CORRECT ANSWER Devices with low data transfer demand can use a single lane,
and devices with higher requirements can increase their available data transfer rate by using additional
lanes.
TRUE - CORRECT ANSWER Examples of external I/O buses include USB and FireWire.
TRUE - CORRECT ANSWER A system bus connects computer system components, including
the CPU memory, storage, and I/O devices.
