2025 OCR A-Level Computer Science || with Complete Solution.
Accumulator (ACC) correct answers Holds the results of calculations performed by the ALU.
Checks for conditional branching. Stores data from the MDR/RAM.
Address Bus correct answers A unidirectional pathway that carries memory addresses for data or
instructions.
Arithmetic and Logic Unit (ALU) correct answers Handles arithmetic calculations and logical
operations required for executing instructions.
Buses correct answers Communication pathways that transfer data, addresses to other
components and controls signals between CPU components.
Contemporary Processor Architecture correct answers A modern CPU design that integrates
elements from both Von Neumann and Harvard architectures.
Control Bus correct answers A bi-directional pathway that transmits control signals sent from the
control unit to manage the execution and coordination of instructions in the CPU.
Control Unit (CU) correct answers Sends control signals to coordinate the movement of data
through the processor. It also controls the buses to manage communication between the CPU,
memory, and input/output devices.
Current Instruction Register (CIR) correct answers A register that holds the current instruction
being processed, separating it into operand and opcode.
Data Bus correct answers A bi-directional pathway that carries data between the processor and
memory.
Fetch-Decode-Execute Cycle correct answers The sequence in which the CPU retrieves,
interprets, and executes instructions.
,Harvard Architecture correct answers A computer architecture that separates instruction and data
storage into distinct memory units to improve efficiency. Uses data and address buses.
Memory Address Register (MAR) correct answers Stores the memory address of the current
instruction or data location to be accessed via RAM.
Memory Data Register (MDR) correct answers Holds data that is being read from or written to
memory (RAM) during processing. Sends data/instruction to the current instruction register.
Pipelining correct answers A technique that enables overlapping instruction execution by
fetching the next instruction while processing the current one.
Program Counter (PC) correct answers A register that stores the address of the next instruction to
be executed.
Registers correct answers Small, fast memory units within the CPU that temporarily store data,
instructions, or addresses.
Von Neumann Architecture correct answers A computing model where data and instructions
share the same memory and communication pathways. Not as efficient as Harvard.
Complex Instruction Set Computer (CISC) correct answers A processor architecture designed to
execute complex instructions. Instructions may take multiple clock cycles, instructions are
variable in size in format, limiting pipelining efficiency. Complex circuitry increases cost in
comparison to RISC.
Graphic Processing Unit (GPU) correct answers A specialised processor containing many small
cores optimised for parallel processing, commonly used in graphics rendering, machine learning,
and data processing.
, Multicore Systems correct answers A processor design that integrates multiple CPU cores onto a
single chip, enabling efficient workload distribution and improved performance.
Parallel Processing System correct answers Multiple processors or processor cores work
simultaneously to execute different parts of a task or multiple tasks at the same time, improving
efficiency and reducing execution time.
Reduced Instruction Set Computer (RISC) correct answers A processor architecture that executes
simple instructions within a single clock cycle (higher battery life compare to CISC), allowing
for pipelining but requiring more RAM for program execution. Less complex circuitry reduces
cost.
Fetch correct answers The PC copies the address to the MAR, which is then sent via the Address
Bus. The PC increments, a Read signal is sent via the Control Bus. The RAM places the
instruction on the Data Bus, transferring it to the MDR, then into the CIR for decoding.
Decode correct answers Interprets the fetched instruction. The CIR sends the instruction to the
Control Unit, where the instruction is split into opcode and operand. The CU then generates
control signals to prepare the necessary registers, buses, and ALU for execution.
Execute correct answers Carries out the decoded instruction. The result is then stored in a
register, memory, or sent to an output device.
Clock Speed correct answers The rate at which the processor's internal clock generates pulses,
affecting how quickly instructions are executed. Higher clock speeds leads to more cycles per
second.
Number of Cores correct answers The number of processing units in a CPU, allowing multiple
instructions to be executed simultaneously, increasing performance.
Cache correct answers A small, high-speed memory within the CPU that stores frequently used
instructions and data. Quicker to access than RAM, therefore more cache increases performance.
Accumulator (ACC) correct answers Holds the results of calculations performed by the ALU.
Checks for conditional branching. Stores data from the MDR/RAM.
Address Bus correct answers A unidirectional pathway that carries memory addresses for data or
instructions.
Arithmetic and Logic Unit (ALU) correct answers Handles arithmetic calculations and logical
operations required for executing instructions.
Buses correct answers Communication pathways that transfer data, addresses to other
components and controls signals between CPU components.
Contemporary Processor Architecture correct answers A modern CPU design that integrates
elements from both Von Neumann and Harvard architectures.
Control Bus correct answers A bi-directional pathway that transmits control signals sent from the
control unit to manage the execution and coordination of instructions in the CPU.
Control Unit (CU) correct answers Sends control signals to coordinate the movement of data
through the processor. It also controls the buses to manage communication between the CPU,
memory, and input/output devices.
Current Instruction Register (CIR) correct answers A register that holds the current instruction
being processed, separating it into operand and opcode.
Data Bus correct answers A bi-directional pathway that carries data between the processor and
memory.
Fetch-Decode-Execute Cycle correct answers The sequence in which the CPU retrieves,
interprets, and executes instructions.
,Harvard Architecture correct answers A computer architecture that separates instruction and data
storage into distinct memory units to improve efficiency. Uses data and address buses.
Memory Address Register (MAR) correct answers Stores the memory address of the current
instruction or data location to be accessed via RAM.
Memory Data Register (MDR) correct answers Holds data that is being read from or written to
memory (RAM) during processing. Sends data/instruction to the current instruction register.
Pipelining correct answers A technique that enables overlapping instruction execution by
fetching the next instruction while processing the current one.
Program Counter (PC) correct answers A register that stores the address of the next instruction to
be executed.
Registers correct answers Small, fast memory units within the CPU that temporarily store data,
instructions, or addresses.
Von Neumann Architecture correct answers A computing model where data and instructions
share the same memory and communication pathways. Not as efficient as Harvard.
Complex Instruction Set Computer (CISC) correct answers A processor architecture designed to
execute complex instructions. Instructions may take multiple clock cycles, instructions are
variable in size in format, limiting pipelining efficiency. Complex circuitry increases cost in
comparison to RISC.
Graphic Processing Unit (GPU) correct answers A specialised processor containing many small
cores optimised for parallel processing, commonly used in graphics rendering, machine learning,
and data processing.
, Multicore Systems correct answers A processor design that integrates multiple CPU cores onto a
single chip, enabling efficient workload distribution and improved performance.
Parallel Processing System correct answers Multiple processors or processor cores work
simultaneously to execute different parts of a task or multiple tasks at the same time, improving
efficiency and reducing execution time.
Reduced Instruction Set Computer (RISC) correct answers A processor architecture that executes
simple instructions within a single clock cycle (higher battery life compare to CISC), allowing
for pipelining but requiring more RAM for program execution. Less complex circuitry reduces
cost.
Fetch correct answers The PC copies the address to the MAR, which is then sent via the Address
Bus. The PC increments, a Read signal is sent via the Control Bus. The RAM places the
instruction on the Data Bus, transferring it to the MDR, then into the CIR for decoding.
Decode correct answers Interprets the fetched instruction. The CIR sends the instruction to the
Control Unit, where the instruction is split into opcode and operand. The CU then generates
control signals to prepare the necessary registers, buses, and ALU for execution.
Execute correct answers Carries out the decoded instruction. The result is then stored in a
register, memory, or sent to an output device.
Clock Speed correct answers The rate at which the processor's internal clock generates pulses,
affecting how quickly instructions are executed. Higher clock speeds leads to more cycles per
second.
Number of Cores correct answers The number of processing units in a CPU, allowing multiple
instructions to be executed simultaneously, increasing performance.
Cache correct answers A small, high-speed memory within the CPU that stores frequently used
instructions and data. Quicker to access than RAM, therefore more cache increases performance.
