EEE 120
QUESTIONS AND VERIFED
CORRECT ANSWERS
GRADED A+ [LATEST] 100%
GUARANTEED PASS
Negative-edge trggered flip-flop - CORRECT ANSWER-The values are read from data when the
clock goes from 1 to 0
Transparent Low Latch - CORRECT ANSWER-When the clock is low, the output will be
transparently outputted
The time the data input must remain stable after the transition from transparent mode to
storage mode is - CORRECT ANSWER-Latch Hold Time
For a positive edge-triggered memory element, the time the data input must be stable before
the positive clock edge is - CORRECT ANSWER-Flip-Flop Set up time
For a positive edge-triggered memory element, the time the data input must remain stable
after the positive clock edge is - CORRECT ANSWER-Flip Flop hold time
The time the data input must be stable before the transition from transparent mode to
storage mode is - CORRECT ANSWER-Latch Set Up Time
A latch is constructed by using multiple flip-flops. - CORRECT ANSWER-False
QUESTIONS AND VERIFED
CORRECT ANSWERS
GRADED A+ [LATEST] 100%
GUARANTEED PASS
Negative-edge trggered flip-flop - CORRECT ANSWER-The values are read from data when the
clock goes from 1 to 0
Transparent Low Latch - CORRECT ANSWER-When the clock is low, the output will be
transparently outputted
The time the data input must remain stable after the transition from transparent mode to
storage mode is - CORRECT ANSWER-Latch Hold Time
For a positive edge-triggered memory element, the time the data input must be stable before
the positive clock edge is - CORRECT ANSWER-Flip-Flop Set up time
For a positive edge-triggered memory element, the time the data input must remain stable
after the positive clock edge is - CORRECT ANSWER-Flip Flop hold time
The time the data input must be stable before the transition from transparent mode to
storage mode is - CORRECT ANSWER-Latch Set Up Time
A latch is constructed by using multiple flip-flops. - CORRECT ANSWER-False
