Ahsanullah University of Science and Technology
Department of Electrical & Electronic Engineering
Assignment: Implementing a Shift Register for Roll
Number Entry
Course No: EEE-2103
Course Name: Digital Circuit Design
Date of Submission: 15 April, 2026
Name: Touki Tahmid Hoque
ID: 00724105131103
Year: 2nd
Semester:1st
Section: B
, Working Principle of Shift Register:
A shift register is a sequential logic circuit primarily used for the storage
and transfer of data. It is constructed from a cascade of D flip-flops,
where the output of one flip-flop is connected to the input of the next,
and all flip-flops share a common clock signal.On each active clock edge
(usually the rising edge), the register performs two actions
simultaneously:
1. It captures the data present at its Serial Input (DS) and stores it in the
first flip-flop.
2. It shifts the data held in each flip-flop to the next one in the chain.
For a Serial-In, Parallel-Out (SIPO) register, the data enters bit-by-bit
(serially) over multiple clock cycles. After N clock cycles, the N bits of
data are present on the N parallel outputs (Q0 to QN-1) and can be read
simultaneously.
ID: 00724105131103
Last 3 digits: 103
Binary Conversion: 01100111
Circuit Diagram:
Department of Electrical & Electronic Engineering
Assignment: Implementing a Shift Register for Roll
Number Entry
Course No: EEE-2103
Course Name: Digital Circuit Design
Date of Submission: 15 April, 2026
Name: Touki Tahmid Hoque
ID: 00724105131103
Year: 2nd
Semester:1st
Section: B
, Working Principle of Shift Register:
A shift register is a sequential logic circuit primarily used for the storage
and transfer of data. It is constructed from a cascade of D flip-flops,
where the output of one flip-flop is connected to the input of the next,
and all flip-flops share a common clock signal.On each active clock edge
(usually the rising edge), the register performs two actions
simultaneously:
1. It captures the data present at its Serial Input (DS) and stores it in the
first flip-flop.
2. It shifts the data held in each flip-flop to the next one in the chain.
For a Serial-In, Parallel-Out (SIPO) register, the data enters bit-by-bit
(serially) over multiple clock cycles. After N clock cycles, the N bits of
data are present on the N parallel outputs (Q0 to QN-1) and can be read
simultaneously.
ID: 00724105131103
Last 3 digits: 103
Binary Conversion: 01100111
Circuit Diagram:
