CPE 323 Final Exam || 100% Exact Solutions.
A. (2 points) (True | False) Interrupt service routines must end with a RET (MOV @SP+, PC)
instruction that retrieves the return address from the top of the stack. correct answers F
B. (2 points) (True | False) The GIE bit in the status register can be set or cleared by the
programmer at any point of time. correct answers T
C. (2 points) (True | False) If multiple interrupt requests are pending at the time of exception
processing, the MSP430 selects the one with the highest priority. correct answers T
D. (2 points) (True | False) The interrupt vector table is filled with the starting addresses of the
ISRs at the time of manufacturing of the microcontroller and its content cannot be changed.
correct answers F
E (2 points) (True | False) The MSP430 automatically resets (in hardware) the relevant interrupt
flags that record pending requests for both single-sourced and multi-sourced interrupt service
routines. correct answers F
A. (2 points) (True | False) The MSP430's clock module produces multiple clock signals that can
be configured insoftware independently from each other. correct answers T
B. (2 points) (True | False) The MSP430 clock signals are active all time regardless of the
operating mode. correct answers F
C. (2 points) (True | False) The watchdog timer (WDT) can be configured in such a way to
timestamp an external hardware event (e.g., rising edge of a signal) without intervention in
software. correct answers F
D. (2 points) (True | False) The watchdog timer supports only several predefined time intervals.
correct answers T
E. (2 points) An MSP430 FLL+ is configured as follows: MCLK = 2,097,152 Hz and ACLK =
32,768 Hz. Howmany MCLK clocks occur in one ACLK clock? correct answers (2^21/2^15
= )64
E. (2 points) (True | False) The number of characters your program can send to the workstation
will dramatically decrease if the workstation starts sending characters to the MSP430 at the same
time. correct answers F
F. (2 points) (True | False) When sending ascii character for '0' (ascii('0')=48), the parity bit P =
1. correct answers F
A. (1 points) (True | False) DMA controller can be initialized to perform a transfer of a block of
data from a memory buffer to a serial communication interface (USCI peripheral). correct
answers T
, An MSP430 development platform is connected to a workstation over a RS232 serial interface.
Assume that MSP430 uses the following UART configuration: baud rate 38,400; 8-bit
characters; 1 stop bit, parity bit is included (even parity). Note: ignore multiprocessing bit. D. (2
points) What is the maximum number of characters you can send in 1 second from the MSP430
to the workstation? correct answers (the number of bits per character: 1 (start) + 8 + 1 (parity) +
1 (stop) = 11 bits per character. the number of characters is less than 38,400 bits/sec / 11 bits
= )3490
A. (2 points) (True | False) When a new interrupt request is received, the processor immediately
stops processing the currently executing instruction (before finishing it) and starts the exception
processing. correct answers F
B. (2 points) (True | False) The RETI (return from interrupt) instruction retrieves both the status
register and the program counter from the stack. correct answers T
C. (2 points) (True | False) If multiple interrupt requests are pending, the processor selects the
one that arrived first. correct answers F
D. (2 points) (True | False) The GIE (Global Interrupt Enable) bit in the status register can be set
inside an interrupt service routine explicitly by the programmer to enable nesting of interrupts.
correct answers T
E. (2 points) (True | False) In case that multiple interrupt request sources share a single entry in
the interrupt vector table, programmers need to explicitly clear interrupt flag bits in the
corresponding service routine. correct answers T
A. (2 points) (True | False) The MSP430's clock module can internally generate clocks used by
the processor and peripherals or use external crystal oscillators. correct answers T
B. (2 points) (True | False) MCLK, SMCLK, and ACLK are fixed and cannot be changed in
software. correct answers F
C. (2 points) (True | False) To prevent a controlled reset of the systems, the watchdog timer in
the watchdog mode requires a hardware signal to clear its control bit before the time period
expires. correct answers F
D. (2 points) (True | False) TimerA can be configured to generate pulse-width modulated signals
without intervention from software. correct answers T
E. (2 points) What does it involve capturing an external event in TimerA (what happens inside
TimerA)? correct answers Current content of the TimerrA counter (TAR) is latched into the one
of the capture and control registers (CCRx).
A. (2 points) (True | False) Interrupt service routines must end with a RET (MOV @SP+, PC)
instruction that retrieves the return address from the top of the stack. correct answers F
B. (2 points) (True | False) The GIE bit in the status register can be set or cleared by the
programmer at any point of time. correct answers T
C. (2 points) (True | False) If multiple interrupt requests are pending at the time of exception
processing, the MSP430 selects the one with the highest priority. correct answers T
D. (2 points) (True | False) The interrupt vector table is filled with the starting addresses of the
ISRs at the time of manufacturing of the microcontroller and its content cannot be changed.
correct answers F
E (2 points) (True | False) The MSP430 automatically resets (in hardware) the relevant interrupt
flags that record pending requests for both single-sourced and multi-sourced interrupt service
routines. correct answers F
A. (2 points) (True | False) The MSP430's clock module produces multiple clock signals that can
be configured insoftware independently from each other. correct answers T
B. (2 points) (True | False) The MSP430 clock signals are active all time regardless of the
operating mode. correct answers F
C. (2 points) (True | False) The watchdog timer (WDT) can be configured in such a way to
timestamp an external hardware event (e.g., rising edge of a signal) without intervention in
software. correct answers F
D. (2 points) (True | False) The watchdog timer supports only several predefined time intervals.
correct answers T
E. (2 points) An MSP430 FLL+ is configured as follows: MCLK = 2,097,152 Hz and ACLK =
32,768 Hz. Howmany MCLK clocks occur in one ACLK clock? correct answers (2^21/2^15
= )64
E. (2 points) (True | False) The number of characters your program can send to the workstation
will dramatically decrease if the workstation starts sending characters to the MSP430 at the same
time. correct answers F
F. (2 points) (True | False) When sending ascii character for '0' (ascii('0')=48), the parity bit P =
1. correct answers F
A. (1 points) (True | False) DMA controller can be initialized to perform a transfer of a block of
data from a memory buffer to a serial communication interface (USCI peripheral). correct
answers T
, An MSP430 development platform is connected to a workstation over a RS232 serial interface.
Assume that MSP430 uses the following UART configuration: baud rate 38,400; 8-bit
characters; 1 stop bit, parity bit is included (even parity). Note: ignore multiprocessing bit. D. (2
points) What is the maximum number of characters you can send in 1 second from the MSP430
to the workstation? correct answers (the number of bits per character: 1 (start) + 8 + 1 (parity) +
1 (stop) = 11 bits per character. the number of characters is less than 38,400 bits/sec / 11 bits
= )3490
A. (2 points) (True | False) When a new interrupt request is received, the processor immediately
stops processing the currently executing instruction (before finishing it) and starts the exception
processing. correct answers F
B. (2 points) (True | False) The RETI (return from interrupt) instruction retrieves both the status
register and the program counter from the stack. correct answers T
C. (2 points) (True | False) If multiple interrupt requests are pending, the processor selects the
one that arrived first. correct answers F
D. (2 points) (True | False) The GIE (Global Interrupt Enable) bit in the status register can be set
inside an interrupt service routine explicitly by the programmer to enable nesting of interrupts.
correct answers T
E. (2 points) (True | False) In case that multiple interrupt request sources share a single entry in
the interrupt vector table, programmers need to explicitly clear interrupt flag bits in the
corresponding service routine. correct answers T
A. (2 points) (True | False) The MSP430's clock module can internally generate clocks used by
the processor and peripherals or use external crystal oscillators. correct answers T
B. (2 points) (True | False) MCLK, SMCLK, and ACLK are fixed and cannot be changed in
software. correct answers F
C. (2 points) (True | False) To prevent a controlled reset of the systems, the watchdog timer in
the watchdog mode requires a hardware signal to clear its control bit before the time period
expires. correct answers F
D. (2 points) (True | False) TimerA can be configured to generate pulse-width modulated signals
without intervention from software. correct answers T
E. (2 points) What does it involve capturing an external event in TimerA (what happens inside
TimerA)? correct answers Current content of the TimerrA counter (TAR) is latched into the one
of the capture and control registers (CCRx).
