WGU D386 Hardware and Operating
Systems Essentials Actual Exam
Questions & Verified Answers | Latest
Updated Study Guide
1. Which component of the CPU is responsible for performing arithmetic and
logical operations?
A) Control Unit (CU)
B) Arithmetic Logic Unit (ALU)
C) Cache Memory
D) Registers
Answer: B
Rationale: The Arithmetic Logic Unit (ALU) performs all arithmetic calculations
(addition, subtraction) and logical operations (AND, OR, NOT). The Control Unit
directs data flow, cache is fast memory, and registers store temporary data. This is
frequently confused with the Control Unit.
2. A processor with "quad-core" technology actually contains:
A) Four separate CPU chips on one motherboard
B) Four independent processing units within one CPU package
C) Four levels of cache memory
D) Four threads executing simultaneously
Answer: B
Rationale: Quad-core means four independent processing cores (actual CPUs)
integrated into a single CPU package/chip. They share some resources but can
execute instructions independently. Option A describes multiple CPUs, C describes
cache hierarchy, and D describes threading (which cores support but isn't the
definition).
3. Which cache level is closest to the ALU and has the fastest access speed?
A) L1 Cache
,B) L2 Cache
C) L3 Cache
D) RAM
Answer: A
Rationale: L1 cache is the smallest but fastest cache, located closest to the CPU
cores (often split into instruction and data cache). L2 is larger but slower, L3 is
shared across cores and slower, and RAM is much slower than all cache levels.
Tricky because people assume larger cache is faster.
4. What is the primary function of the CPU's Control Unit?
A) Perform mathematical calculations
B) Store intermediate calculation results
C) Direct the flow of data and instructions within the CPU
D) Provide temporary high-speed storage
Answer: C
Rationale: The Control Unit (CU) acts as the CPU's "traffic director," managing
the flow of data between the ALU, registers, cache, and memory. It decodes
instructions and generates control signals. Option A is the ALU's job, B is
registers, and D is cache.
5. Hyper-threading technology allows a single physical core to:
A) Run at higher clock speeds
B) Appear as two logical cores to the operating system
C) Access more L1 cache
D) Reduce power consumption
Answer: B
Rationale: Hyper-threading (Intel) or similar technology creates virtual/logical
cores from one physical core, allowing the OS to see and schedule tasks to two
logical processors per physical core. This improves multitasking but doesn't
increase clock speed (A), cache (C), or directly reduce power (D).
6. Which factor MOST directly determines how many instructions a CPU can
execute per second?
,A) Number of cores
B) Clock speed (GHz)
C) Cache size
D) Power consumption
Answer: B
Rationale: Clock speed (measured in GHz) directly indicates how many cycles per
second the CPU can execute, with each cycle potentially processing instructions.
More cores (A) help with parallel tasks but not single-instruction speed. Cache (C)
reduces delays but doesn't determine instruction rate. This is tricky because cores
matter for multitasking.
7. What is the main advantage of an ARM processor architecture over x86 in
mobile devices?
A) Higher clock speeds
B) Better compatibility with legacy software
C) Lower power consumption
D) More cores
Answer: C
Rationale: ARM uses a Reduced Instruction Set Computer (RISC) design that
requires fewer transistors and less power than x86's Complex Instruction Set
Computer (CISC), making it ideal for battery-powered devices. ARM typically has
lower clock speeds (A), poorer legacy compatibility (B), and core count varies (D).
8. Which register holds the address of the next instruction to be executed?
A) Accumulator
B) Program Counter (PC)
C) Status Register
D) Memory Address Register
Answer: B
Rationale: The Program Counter (also called Instruction Pointer) stores the
memory address of the next instruction. The Accumulator holds calculation results,
Status Register holds flags (like carry, zero), and Memory Address Register holds
addresses for memory access operations.
, 9. When a CPU experiences a "cache hit," it means:
A) The cache memory crashed
B) The requested data was found in cache
C) The cache size increased
D) Data was written to cache but not RAM
Answer: B
Rationale: A cache hit occurs when the CPU finds the requested data in cache
memory, avoiding the slower RAM access. A "cache miss" means data wasn't in
cache and must be retrieved from RAM. This is a common terminology trap.
10. What is the primary purpose of CPU pipelining?
A) Reduce power consumption
B) Increase cache size
C) Execute multiple instructions simultaneously by overlapping stages
D) Cool the processor faster
Answer: C
Rationale: Pipelining allows the CPU to work on multiple instructions at different
stages (fetch, decode, execute, writeback) simultaneously, increasing throughput. It
doesn't directly affect power (A), cache (B), or cooling (D). Tricky because it's
about overlapping, not true parallel execution like multi-core.
11. Which technology allows a CPU to dynamically adjust its clock speed
based on workload?
A) Hyper-threading
B) Intel SpeedStep / AMD PowerPlay
C) RAID
D) DMA
Answer: B
Rationale: SpeedStep (Intel) or PowerPlay (AMD) dynamically adjusts clock
speed and voltage to save power during light loads and increase performance
during heavy loads. Hyper-threading (A) creates logical cores, RAID (C) is storage
redundancy, and DMA (D) is memory access without CPU.
Systems Essentials Actual Exam
Questions & Verified Answers | Latest
Updated Study Guide
1. Which component of the CPU is responsible for performing arithmetic and
logical operations?
A) Control Unit (CU)
B) Arithmetic Logic Unit (ALU)
C) Cache Memory
D) Registers
Answer: B
Rationale: The Arithmetic Logic Unit (ALU) performs all arithmetic calculations
(addition, subtraction) and logical operations (AND, OR, NOT). The Control Unit
directs data flow, cache is fast memory, and registers store temporary data. This is
frequently confused with the Control Unit.
2. A processor with "quad-core" technology actually contains:
A) Four separate CPU chips on one motherboard
B) Four independent processing units within one CPU package
C) Four levels of cache memory
D) Four threads executing simultaneously
Answer: B
Rationale: Quad-core means four independent processing cores (actual CPUs)
integrated into a single CPU package/chip. They share some resources but can
execute instructions independently. Option A describes multiple CPUs, C describes
cache hierarchy, and D describes threading (which cores support but isn't the
definition).
3. Which cache level is closest to the ALU and has the fastest access speed?
A) L1 Cache
,B) L2 Cache
C) L3 Cache
D) RAM
Answer: A
Rationale: L1 cache is the smallest but fastest cache, located closest to the CPU
cores (often split into instruction and data cache). L2 is larger but slower, L3 is
shared across cores and slower, and RAM is much slower than all cache levels.
Tricky because people assume larger cache is faster.
4. What is the primary function of the CPU's Control Unit?
A) Perform mathematical calculations
B) Store intermediate calculation results
C) Direct the flow of data and instructions within the CPU
D) Provide temporary high-speed storage
Answer: C
Rationale: The Control Unit (CU) acts as the CPU's "traffic director," managing
the flow of data between the ALU, registers, cache, and memory. It decodes
instructions and generates control signals. Option A is the ALU's job, B is
registers, and D is cache.
5. Hyper-threading technology allows a single physical core to:
A) Run at higher clock speeds
B) Appear as two logical cores to the operating system
C) Access more L1 cache
D) Reduce power consumption
Answer: B
Rationale: Hyper-threading (Intel) or similar technology creates virtual/logical
cores from one physical core, allowing the OS to see and schedule tasks to two
logical processors per physical core. This improves multitasking but doesn't
increase clock speed (A), cache (C), or directly reduce power (D).
6. Which factor MOST directly determines how many instructions a CPU can
execute per second?
,A) Number of cores
B) Clock speed (GHz)
C) Cache size
D) Power consumption
Answer: B
Rationale: Clock speed (measured in GHz) directly indicates how many cycles per
second the CPU can execute, with each cycle potentially processing instructions.
More cores (A) help with parallel tasks but not single-instruction speed. Cache (C)
reduces delays but doesn't determine instruction rate. This is tricky because cores
matter for multitasking.
7. What is the main advantage of an ARM processor architecture over x86 in
mobile devices?
A) Higher clock speeds
B) Better compatibility with legacy software
C) Lower power consumption
D) More cores
Answer: C
Rationale: ARM uses a Reduced Instruction Set Computer (RISC) design that
requires fewer transistors and less power than x86's Complex Instruction Set
Computer (CISC), making it ideal for battery-powered devices. ARM typically has
lower clock speeds (A), poorer legacy compatibility (B), and core count varies (D).
8. Which register holds the address of the next instruction to be executed?
A) Accumulator
B) Program Counter (PC)
C) Status Register
D) Memory Address Register
Answer: B
Rationale: The Program Counter (also called Instruction Pointer) stores the
memory address of the next instruction. The Accumulator holds calculation results,
Status Register holds flags (like carry, zero), and Memory Address Register holds
addresses for memory access operations.
, 9. When a CPU experiences a "cache hit," it means:
A) The cache memory crashed
B) The requested data was found in cache
C) The cache size increased
D) Data was written to cache but not RAM
Answer: B
Rationale: A cache hit occurs when the CPU finds the requested data in cache
memory, avoiding the slower RAM access. A "cache miss" means data wasn't in
cache and must be retrieved from RAM. This is a common terminology trap.
10. What is the primary purpose of CPU pipelining?
A) Reduce power consumption
B) Increase cache size
C) Execute multiple instructions simultaneously by overlapping stages
D) Cool the processor faster
Answer: C
Rationale: Pipelining allows the CPU to work on multiple instructions at different
stages (fetch, decode, execute, writeback) simultaneously, increasing throughput. It
doesn't directly affect power (A), cache (B), or cooling (D). Tricky because it's
about overlapping, not true parallel execution like multi-core.
11. Which technology allows a CPU to dynamically adjust its clock speed
based on workload?
A) Hyper-threading
B) Intel SpeedStep / AMD PowerPlay
C) RAID
D) DMA
Answer: B
Rationale: SpeedStep (Intel) or PowerPlay (AMD) dynamically adjusts clock
speed and voltage to save power during light loads and increase performance
during heavy loads. Hyper-threading (A) creates logical cores, RAID (C) is storage
redundancy, and DMA (D) is memory access without CPU.
