WGU D386 Hardware and Operating Systems
Essentials ACTUAL EXAM 2026–2027 |
Complete Questions & Verified Answers | Latest
Updated A+ Study Guide
1. Which CPU register is responsible for holding the address of the next instruction
to be executed?
A) Memory Data Register (MDR)
B) Accumulator (ACC)
C) Program Counter (PC)
D) Instruction Register (IR)
Rationale: The Program Counter holds the memory address of the next
instruction. After fetching, the PC increments or is updated by branch instructions.
2. A temporary storage location inside the CPU that holds data fetched from
memory or data waiting to be written to memory is called:
A) Memory Data Register (MDR)
B) Memory Address Register (MAR)
C) Cache Controller
D) Status Register
Rationale: The MDR holds the actual data being transferred to/from memory. The
MAR holds the address of that data.
3. Which cache level is smallest in size but closest to the CPU core?
A) L3 Cache
B) L2 Cache
C) L1 Cache
D) Main Memory
Rationale: L1 cache is typically 16KB–128KB per core and is the fastest, smallest
cache closest to the core.
,4. A system has a unified L2 cache. This means:
A) L2 holds only data, not instructions
B) L2 holds only instructions, not data
C) L2 holds both data and instructions
D) L2 is disabled when L1 is present
Rationale: Unified cache stores both data and instructions. Split caches (like
typical L1) separate them.
5. Which memory type is used for L1 cache?
A) Dynamic RAM (DRAM)
B) Static RAM (SRAM)
C) Flash memory
D) EEPROM
Rationale: SRAM is faster and more expensive than DRAM, making it suitable
for CPU caches.
6. A CPU has an L1 miss. It next checks:
A) Main Memory (RAM)
B) Hard Disk
C) L2 Cache
D) L3 Cache (if present)
Rationale: The typical hierarchy: L1 → L2 → L3 → RAM. L2 is checked
immediately after L1 miss.
7. Which component translates virtual addresses to physical addresses?
A) Memory Management Unit (MMU)
B) Arithmetic Logic Unit (ALU)
C) Control Unit (CU)
D) Floating Point Unit (FPU)
Rationale: The MMU handles address translation and memory protection.
,8. A system with 8 CPU cores features 2MB of L3 cache shared among all cores.
What is a primary benefit of shared L3?
A) Faster context switching
B) Reduced cache misses when threads share data
C) Larger L1 per core
D) Lower power consumption
Rationale: Shared last-level cache allows cores to access common data without
going to RAM.
9. Which register holds the result of an arithmetic operation?
A) Accumulator (ACC)
B) Memory Buffer Register (MBR)
C) Index Register
D) Stack Pointer
Rationale: The accumulator temporarily stores results from the ALU.
10. A CPU advertises a "2.5 GHz clock speed." What does this measure?
A) Cache size
B) Cycles per second
C) Data bus width
D) Number of cores
Rationale: Clock speed is cycles per second (2.5 billion cycles/sec).
11. In a Harvard architecture system:
A) Separate buses and caches for instructions and data
B) Unified memory for code and data
C) No cache memory
D) Only one register set
Rationale: Harvard architecture physically separates instruction and data memory.
, 12. Which cache level is typically the slowest but largest?
A) L1
B) L2
C) L3
D) Register file
Rationale: L3 is larger and slower than L1/L2 but faster than RAM.
13. A developer notices that frequently accessing an array in column-major order
on a row-major system causes many cache misses. This is an example of:
A) Cache thrashing
B) Poor spatial locality
C) Write-through penalty
D) TLB miss
Rationale: Row-major layout favors row access; column access skips between
rows, reducing spatial locality.
14. Which register holds the memory address that the CPU is about to read from or
write to?
A) Memory Address Register (MAR)
B) Memory Data Register (MDR)
C) Instruction Register
D) Program Counter
Rationale: The MAR holds the address; the MDR holds the data at that address.
15. A CPU supports simultaneous multithreading (SMT). What is the primary
benefit?
A) Increased cache size
B) Better utilization of execution units
C) Reduced clock speed
D) Larger addressable memory
Rationale: SMT allows one core to run multiple threads, hiding latency and using
idle execution units.
Essentials ACTUAL EXAM 2026–2027 |
Complete Questions & Verified Answers | Latest
Updated A+ Study Guide
1. Which CPU register is responsible for holding the address of the next instruction
to be executed?
A) Memory Data Register (MDR)
B) Accumulator (ACC)
C) Program Counter (PC)
D) Instruction Register (IR)
Rationale: The Program Counter holds the memory address of the next
instruction. After fetching, the PC increments or is updated by branch instructions.
2. A temporary storage location inside the CPU that holds data fetched from
memory or data waiting to be written to memory is called:
A) Memory Data Register (MDR)
B) Memory Address Register (MAR)
C) Cache Controller
D) Status Register
Rationale: The MDR holds the actual data being transferred to/from memory. The
MAR holds the address of that data.
3. Which cache level is smallest in size but closest to the CPU core?
A) L3 Cache
B) L2 Cache
C) L1 Cache
D) Main Memory
Rationale: L1 cache is typically 16KB–128KB per core and is the fastest, smallest
cache closest to the core.
,4. A system has a unified L2 cache. This means:
A) L2 holds only data, not instructions
B) L2 holds only instructions, not data
C) L2 holds both data and instructions
D) L2 is disabled when L1 is present
Rationale: Unified cache stores both data and instructions. Split caches (like
typical L1) separate them.
5. Which memory type is used for L1 cache?
A) Dynamic RAM (DRAM)
B) Static RAM (SRAM)
C) Flash memory
D) EEPROM
Rationale: SRAM is faster and more expensive than DRAM, making it suitable
for CPU caches.
6. A CPU has an L1 miss. It next checks:
A) Main Memory (RAM)
B) Hard Disk
C) L2 Cache
D) L3 Cache (if present)
Rationale: The typical hierarchy: L1 → L2 → L3 → RAM. L2 is checked
immediately after L1 miss.
7. Which component translates virtual addresses to physical addresses?
A) Memory Management Unit (MMU)
B) Arithmetic Logic Unit (ALU)
C) Control Unit (CU)
D) Floating Point Unit (FPU)
Rationale: The MMU handles address translation and memory protection.
,8. A system with 8 CPU cores features 2MB of L3 cache shared among all cores.
What is a primary benefit of shared L3?
A) Faster context switching
B) Reduced cache misses when threads share data
C) Larger L1 per core
D) Lower power consumption
Rationale: Shared last-level cache allows cores to access common data without
going to RAM.
9. Which register holds the result of an arithmetic operation?
A) Accumulator (ACC)
B) Memory Buffer Register (MBR)
C) Index Register
D) Stack Pointer
Rationale: The accumulator temporarily stores results from the ALU.
10. A CPU advertises a "2.5 GHz clock speed." What does this measure?
A) Cache size
B) Cycles per second
C) Data bus width
D) Number of cores
Rationale: Clock speed is cycles per second (2.5 billion cycles/sec).
11. In a Harvard architecture system:
A) Separate buses and caches for instructions and data
B) Unified memory for code and data
C) No cache memory
D) Only one register set
Rationale: Harvard architecture physically separates instruction and data memory.
, 12. Which cache level is typically the slowest but largest?
A) L1
B) L2
C) L3
D) Register file
Rationale: L3 is larger and slower than L1/L2 but faster than RAM.
13. A developer notices that frequently accessing an array in column-major order
on a row-major system causes many cache misses. This is an example of:
A) Cache thrashing
B) Poor spatial locality
C) Write-through penalty
D) TLB miss
Rationale: Row-major layout favors row access; column access skips between
rows, reducing spatial locality.
14. Which register holds the memory address that the CPU is about to read from or
write to?
A) Memory Address Register (MAR)
B) Memory Data Register (MDR)
C) Instruction Register
D) Program Counter
Rationale: The MAR holds the address; the MDR holds the data at that address.
15. A CPU supports simultaneous multithreading (SMT). What is the primary
benefit?
A) Increased cache size
B) Better utilization of execution units
C) Reduced clock speed
D) Larger addressable memory
Rationale: SMT allows one core to run multiple threads, hiding latency and using
idle execution units.
