Exam VHDL

Create a VHDL of Half Subtractor using Behavioral Modelling.
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

entity half_subtractor_tb is
end half_subtractor_tb;

architecture behave of half_subtractor_tb is

signal r_a : bit :='0';
signal r_b : bit :='0';
signal r_diff :bit;
signal r_borrow :bit;

component half_subtractor is
port(
a : in bit;
b: in bit;
diff: out bit;
borrow: out bit
);
end component half_subtractor;

begin
half_subtractor_INST : half_subtractor
port map(
a=> r_a,
b=> r_b,
diff=> r_diff,
borrow=> r_borrow
);

process is
begin
r_a<='0';
r_b<='0';
wait for 10 ns;
r_a<='0';
r_b<='1';
wait for 10 ns;
r_a<='1';
r_b<='0';
wait for 10 ns;
r_a<='1';
r_b<='1';
wait for 10 ns;
end process;

end behave;
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