Exam (elaborations) TEST BANK FOR Computer Organization and Design - The Hardware Software Interface 2nd Edition By David A. Patterson, John L. Hennessy (Solution Manual)-Converted

P ersonal computer (includes workstation and laptop): Personal computers emphasize delivery of good performance to single users at low cost and usually execute third-party soft ware. Personal mobile device (PMD, includes tablets): PMDs are battery operated with wireless connectivity to the Internet and typically cost hundreds of dollars, and, like PCs, users can download soft ware (“apps”) to run on them. Unlike PCs, they no longer have a keyboard and mouse, and are more likely to rely on a touch-sensitive screen or even speech input. Server: Computer used to run large problems and usually accessed via a network. Warehouse-scale computer: Th ousands of processors forming a large cluster. Supercomputer: Computer composed of hundreds to thousands of processors and terabytes of memory. Embedded computer: Computer designed to run one application or one set of related applications and integrated into a single system. 1.2 a. Performance via Pipelining b. Dependability via Redundancy c. Performance via Prediction d. Make the Common Case Fast e. Hierarchy of Memories f. Performance via Parallelism g. Design for Moore’s Law h. Use Abstraction to Simplify Design 1.3 Th e program is compiled into an assembly language program, which is then assembled into a machine language program. 1.4 a. 1280 × 1024 pixels = 1,310,720 pixels = 1,310,720 × 3 = 3,932,160 bytes/ frame. b. 3,932,160 bytes × (8 bits/byte) /100E6 bits/second = 0.31 seconds 1.5 a. performance of P1 (instructions/sec) = 3 × 10 9 /1.5 = 2 × 10 9 performance of P2 (instructions/sec) = 2.5 × 10 9 /1.0 = 2.5 × 10 9 performance of P3 (instructions/sec) = 4 × 10 9 /2.2 = 1.8 × 10 9 S-4 Chapter 1 Solutions b. cycles(P1) = 10 × 3 × 10 9 = 30 × 10 9 s cycles(P2) = 10 × 2.5 × 10 9 = 25 × 10 9 s cycles(P3) = 10 × 4 × 10 9 = 40 × 10 9 s c. No. instructions(P1) = 30 × 10 9 /1.5 = 20 × 10 9 No. instructions(P2) = 25 × 10 9 /1 = 25 × 10 9 No. instructions(P3) = 40 × 10 9 /2.2 = 18.18 × 10 9 CPI new = CPI old × 1.2, then CPI(P1) = 1.8, CPI(P2) = 1.2, CPI(P3) = 2.6 f = No. instr. × CPI/time, then f (P1) = 20 × 10 9 × 1.8/7 = 5.14 GHz f (P2) = 25 × 10 9 × 1.2/7 = 4.28 GHz f (P1) = 18.18 × 10 9 × 2.6/7 = 6.75 GHz 1.6 a. Class A: 10 5 instr. Class B: 2 × 10 5 instr. Class C: 5 × 10 5 instr. Class D: 2 × 10 5 instr. Time = No. instr. × CPI/clock rate Total time P1 = (10 5 + 2 × 10 5 × 2 + 5 × 10 5 × 3 + 2 × 10 5 × 3)/(2.5 × 10 9 ) = 10.4 × 10 −4 s Total time P2 = (10 5 × 2 + 2 × 10 5 × 2 + 5 × 10 5 × 2 + 2 × 10 5 × 2)/(3 × 10 9 ) = 6.66 × 10 −4 s CPI(P1) = 10.4 × 10 −4 × 2.5 × 10 9 /10 6 = 2.6 CPI(P2) = 6.66 × 10 −4 × 3 × 10 9 /10 6 = 2.0 b. clock cycles(P1) = 10 5 × 1 + 2 × 10 5 × 2 + 5 × 10 5 × 3 + 2 × 10 5 × 3 = 26 × 10 5 clock cycles(P2) = 10 5 × 2 + 2 × 10 5 × 2 + 5 × 10 5 × 2 + 2 × 10 5 × 2 = 20 × 10 5 1.7 a. CPI = T exec × f/No. instr. Compiler A CPI = 1.1 Compiler B CPI = 1.25 b. f B /f A = (No. instr.(B) × CPI(B))/(No. instr.(A) × CPI(A)) = 1.37 c. T A /T new = 1.67 T B /T new = 2.27 Chapter 1 Solutions S-5 1.8 1.8.1 C = 2 × DP/(V 2 × F) Pentium 4: C = 3.2E–8F Core i5 Ivy Bridge: C = 2.9E–8F 1.8.2 Pentium 4: 10/100 = 10% Core i5 Ivy Bridge: 30/70 = 42.9% 1.8.3 (S new + D new )/(S old + D old ) = 0.90 D new = C × V new 2 × F S old = V old × I S new = V new × I Therefore: V new = [D new /(C × F)] 1/2 D new = 0.90 × (S old + D old ) − S new S new = V new × (S old /V old ) Pentium 4: S new = V new × (10/1.25) = V new × 8 D new = 0.90 × 100 − V new × 8 = 90 − V new × 8 V new = [(90 − V new × 8)/(3.2E8 × 3.6E9)] 1/2 V new = 0.85 V Core i5: S new = V new × (30/0.9) = V new × 33.3 D new = 0.90 × 70 − V new × 33.3 = 63 − V new × 33.3 V new = [(63 − V new × 33.3)/(2.9E8 × 3.4E9)] 1/2 V new = 0.64 V 1.9 1.9.1 S-6 Chapter 1 Solutions 1.9.2 1.9.3 3 1.10 1.10.1 die area 15cm = wafer area/dies per wafer = π × 7.5 2 /84 = 2.10 cm 2 yield 15cm = 1/(1 + (0.020 × 2.10/2)) 2 = 0.9593 die area 20cm = wafer area/dies per wafer = π × 10 2 /100 = 3.14 cm 2 yield 20cm = 1/(1 + (0.031 × 3.14/2)) 2 = 0.9093 1.10.2 cost/die 15cm = 12/(84 × 0.9593) = 0.1489 cost/die 20cm = 15/(100 × 0.9093) = 0.1650 1.10.3 die area 15cm = wafer area/dies per wafer = π × 7.5 2 /(84 × 1.1) = 1.91 cm 2 yield 15cm = 1/(1 + (0.020 × 1.15 × 1.91/2)) 2 = 0.9575 die area 20cm = wafer area/dies per wafer = π × 10 2 /(100 × 1.1) = 2.86 cm 2 yield 20cm = 1/(1 + (0.03 × 1.15 × 2.86/2)) 2 = 0.9082 1.10.4 defects per area 0.92 = (1–y .5 )/(y .5 × die_area/2) = (1 − 0.92 .5 )/ (0.92 .5 × 2/2) = 0.043 defects/cm 2 defects per area 0.95 = (1–y .5 )/(y .5 × die_area/2) = (1 − 0.95 .5 )/ (0.95 .5 × 2/2) = 0.026 defects/cm 2 1.11 1.11.1 CPI = clock rate × CPU time/instr. count clock rate = 1/cycle time = 3 GHz CPI(bzip2) = 3 × 10 9 × 750/(2389 × 10 9 ) = 0.94 1.11.2 SPEC ratio = ref. time/execution time SPEC ratio(bzip2) = 9 650/750 = 12.86 1.11.3 CPU time = No. instr. × CPI/clock rate If CPI and clock rate do not change, the CPU time increase is equal to the increase in the number of instructions, that is 10%. Chapter 1 Solutions S-7 1.11.4 CPU time(before) = No. instr. × CPI/clock rate CPU time(aft er) = 1.1 × No