UNIT-V
Introduction to Testing
Faults in digital circuits
The increased complexity of integrated circuits (ICs) may cause the degradation of performance
due to defects and faults. In order to have smooth functionality and defect-free circuit and
devices, the testing and observability of ICs need to be grown for deep submicron technology.
Technology enhancement and higher complexity of IC become the bottleneck for the circuit to
work correctly and difficult to test due to the faster clock speed. Therefore, the demand of delay
testing and timing analysis are tremendously increased due to the higher operating frequency and
miniaturization of technology. In general, the testing of circuit and devices can be done based on
the three ways such as verification testing, manufacturing testing, and acceptance testing. The
correctness of the circuits and devices can be done with the help of verification testing. The logic
faults, parametric faults, and physical faults during the manufacturing of an IC can be done using
the manufacturing test. The quality of the product and devices supplied by the VLSI industry
need to be verified and accepted by the user only after completing the acceptance test or
performing incoming inspection. Recently, several works consist of fault simulation, test
generation, design methodology, and synthesis for testability. Therefore, this chapter provides a
detailed information and understanding regarding the testing, observability, and various fault
models.
The increased complexity of integrated circuits (ICs) may cause the degradation of performance
due to defects and faults. In order to have smooth functionality and defect-free circuit and
devices, the testing and observability of ICs need to be grown for deep submicron technology.
Technology enhancement and higher complexity of IC become the bottleneck for the circuit to
work correctly and difficult to test due to the faster clock speed. Therefore, the demand of delay
testing and timing analysis are tremendously increased due to the higher operating frequency and
miniaturization of technology. In general, the testing of circuit and devices can be done based on
the three ways such as verification testing, manufacturing testing, and acceptance testing. The
correctness of the circuits and devices can be done with the help of verification testing. The logic
faults, parametric faults, and physical faults during the manufacturing of an IC can be done using
the manufacturing test. The quality of the product and devices supplied by the VLSI industry
need to be verified and accepted by the user only after completing the acceptance test or
performing incoming inspection. Recently, several works consist of fault simulation, test
generation, design methodology, and synthesis for testability. Therefore, this chapter provides a
detailed information and understanding regarding the testing, observability, and various fault
models.
In order to check the performance and correct functionality of fabricated chips, first, it has to go
through the testing process done within the lab environment. The lab environment is carefully
arranged based on the requirements that should have the following features:
1. Power dissipation by the whole circuit needs to be measured by varying the supply voltage,
VDD.
2. All the analog and digital input and output pins are examined for any malfunctions by
providing real-world signal.
3. Stability of an input clock signal is required to monitor.
, 4. Slow and fast data transfer and exchange through the PCI is required to examine.
Modelling of Faults
Manufacturing of circuits and devices has to go through several testing procedures with the help
of various fault models due to stressful operating condition. With the help of fault models, the
input test vectors are applied to Device Under Test (DUT) or Circuit Under Test (CUT) and
compared it with the golden device/circuit. The faults can occur due to either physical and
manufacturing defects or electrical faults that are described below.
Stuck-At Faults
In the Stuck-At model, a faulty gate input is modeled as a stuck at zero (Stuck-At-0, S-A- 0) or
stuck at one (Stuck-At-l, S-A-l). This model dates from board-level designs, where it was
determined to be adequate for modeling faults. Figure 1 illustrates how an S-A-0 or S-A-1 fault
might occur. These faults most frequently occur due to gate oxide shorts (the nMOS gate to
GND or the pMOS gate to VDD) or metal-to-metal shorts.
FIGURE 1 CMOS stuck-at faults
Short-Circuit and Open-Circuit Faults
Other models include stuck-open or shorted models. Two bridging or shorted faults are shown in
Figure 2. The short S1 results in an S-A-0 fault at input A, while short S2 modifies the function
of the gate. It is evident that to ensure the most accurate modeling, faults should be modeled at
the transistor level because it is only at this level that the complete circuit structure is known. For
instance, in the case of a simple NAND gate, the intermediate node between the series nMOS
transistors is hidden by the schematic. This implies that test generation should ideally take
account of possible shorts and open circuits at the switch level. Expediency dictates that most
existing systems rely on Boolean logic representations of circuits and stuck-at fault modeling.
Introduction to Testing
Faults in digital circuits
The increased complexity of integrated circuits (ICs) may cause the degradation of performance
due to defects and faults. In order to have smooth functionality and defect-free circuit and
devices, the testing and observability of ICs need to be grown for deep submicron technology.
Technology enhancement and higher complexity of IC become the bottleneck for the circuit to
work correctly and difficult to test due to the faster clock speed. Therefore, the demand of delay
testing and timing analysis are tremendously increased due to the higher operating frequency and
miniaturization of technology. In general, the testing of circuit and devices can be done based on
the three ways such as verification testing, manufacturing testing, and acceptance testing. The
correctness of the circuits and devices can be done with the help of verification testing. The logic
faults, parametric faults, and physical faults during the manufacturing of an IC can be done using
the manufacturing test. The quality of the product and devices supplied by the VLSI industry
need to be verified and accepted by the user only after completing the acceptance test or
performing incoming inspection. Recently, several works consist of fault simulation, test
generation, design methodology, and synthesis for testability. Therefore, this chapter provides a
detailed information and understanding regarding the testing, observability, and various fault
models.
The increased complexity of integrated circuits (ICs) may cause the degradation of performance
due to defects and faults. In order to have smooth functionality and defect-free circuit and
devices, the testing and observability of ICs need to be grown for deep submicron technology.
Technology enhancement and higher complexity of IC become the bottleneck for the circuit to
work correctly and difficult to test due to the faster clock speed. Therefore, the demand of delay
testing and timing analysis are tremendously increased due to the higher operating frequency and
miniaturization of technology. In general, the testing of circuit and devices can be done based on
the three ways such as verification testing, manufacturing testing, and acceptance testing. The
correctness of the circuits and devices can be done with the help of verification testing. The logic
faults, parametric faults, and physical faults during the manufacturing of an IC can be done using
the manufacturing test. The quality of the product and devices supplied by the VLSI industry
need to be verified and accepted by the user only after completing the acceptance test or
performing incoming inspection. Recently, several works consist of fault simulation, test
generation, design methodology, and synthesis for testability. Therefore, this chapter provides a
detailed information and understanding regarding the testing, observability, and various fault
models.
In order to check the performance and correct functionality of fabricated chips, first, it has to go
through the testing process done within the lab environment. The lab environment is carefully
arranged based on the requirements that should have the following features:
1. Power dissipation by the whole circuit needs to be measured by varying the supply voltage,
VDD.
2. All the analog and digital input and output pins are examined for any malfunctions by
providing real-world signal.
3. Stability of an input clock signal is required to monitor.
, 4. Slow and fast data transfer and exchange through the PCI is required to examine.
Modelling of Faults
Manufacturing of circuits and devices has to go through several testing procedures with the help
of various fault models due to stressful operating condition. With the help of fault models, the
input test vectors are applied to Device Under Test (DUT) or Circuit Under Test (CUT) and
compared it with the golden device/circuit. The faults can occur due to either physical and
manufacturing defects or electrical faults that are described below.
Stuck-At Faults
In the Stuck-At model, a faulty gate input is modeled as a stuck at zero (Stuck-At-0, S-A- 0) or
stuck at one (Stuck-At-l, S-A-l). This model dates from board-level designs, where it was
determined to be adequate for modeling faults. Figure 1 illustrates how an S-A-0 or S-A-1 fault
might occur. These faults most frequently occur due to gate oxide shorts (the nMOS gate to
GND or the pMOS gate to VDD) or metal-to-metal shorts.
FIGURE 1 CMOS stuck-at faults
Short-Circuit and Open-Circuit Faults
Other models include stuck-open or shorted models. Two bridging or shorted faults are shown in
Figure 2. The short S1 results in an S-A-0 fault at input A, while short S2 modifies the function
of the gate. It is evident that to ensure the most accurate modeling, faults should be modeled at
the transistor level because it is only at this level that the complete circuit structure is known. For
instance, in the case of a simple NAND gate, the intermediate node between the series nMOS
transistors is hidden by the schematic. This implies that test generation should ideally take
account of possible shorts and open circuits at the switch level. Expediency dictates that most
existing systems rely on Boolean logic representations of circuits and stuck-at fault modeling.
