UNIT-IV
Semiconductor Memories
Semiconductor memory arrays capable of storing large quantities of digital information are
essential to all digital systems. The amount of memory required in a particular system depends
on the type of application, but, in general, the number of transistors utilized for the information
(data) storage function is much larger than the number of transistors used in logic operations and
for other purposes. The ever-increasing demand for larger data storage capacity has driven the
fabrication technology and memory development towards more compact design rules and,
consequently, toward higher data storage densities. Thus, the maximum realizable data storage
capacity of single-chip semiconductor memory arrays approximately doubles every two years.
On-chip memory arrays have become widely used subsystems in many VLSI circuits, and
commercially available single-chip read/write memory capacity has reached 64 megabits. This
trend toward higher memory density and larger storage capacity will continue to push the
leading edge of digital system design.
The area efficiency of the memory array, i.e., the number of stored data bits per unit area, is one
of the key design criteria that determine the overall storage capacity and, hence, the memory cost
per bit. Another important issue is the memory access time, i.e., the time required to store and/or
retrieve a particular data bit in the memory array. The access time determines the memory speed,
which is an important performance criterion of the memory array. Finally, the static and dynamic
power consumption of the memory array is a significant factor to be considered in the design,
because of the increasing importance of low-power applications. In the following, we will
investigate different types of MOS memory arrays and discuss in detail the issues of area, speed,
and power consumption for each circuit type.
Memory circuits are generally classified according to the type of data storage and the type of
data access. Read-Only Memory (ROM) circuits allow, as the name implies, only the retrieval of
previously stored data and do not permit modifications of the stored information contents during
normal operation. ROMs are non-volatile memories, i.e., the data storage function is not lost
even when the power supply voltage is off. Depending on the type of data storage (data write)
method, ROMs are classified as mask-programmed ROMs, Programmable ROMs (PROM),
Erasable PROMs (EPROM), and Electrically Erasable PROMs (EEPROM).
Figure 1. Overview of semiconductor memory types.
Read-write (R/W) memory circuits, on the other hand, must permit the modification (writing) of
data bits stored in the memory array, as well as their retrieval (reading) on demand. This requires
that the data storage function be volatile, i.e., the stored data are lost when the power supply
voltage is turned off. The read-write memory circuit is commonly called Random Access
Memory (RAM), mostly due to historical reasons. Compared to sequential-access memories such
, as magnetic tapes, any cell in the R/W memory array can be accessed with nearly equal access
time. Based on the operation type of individual data storage cells, RAMs are classified into two
main categories: Static RAMs (SRAM) and Dynamic RAMs (DRAM). Figure 1 shows an
overview of the different memory types and their classifications.
A typical memory array organization is shown in Fig. 2. The data storage structure, or core,
consists of individual memory cells arranged in an array of horizontal rows and vertical
columns. Each cell is capable of storing one bit of binary information. Also, each memory cell
shares a common connection with the other cells in the same row, and another common
connection with the other cells in the same column. In this structure, there are 2N rows, also
called word lines, and 2M columns, also called bit lines. Thus, the total number of memory cells
in this array is 2M x 2N.
Figure 2. Typical random-access memory array organization.
To access a particular memory cell, i.e., a particular data bit in this array, the corresponding bit
line and the corresponding word line must be activated (selected). The row and column selection
operations are accomplished by row and column decoders, respectively. The row decoder circuit
selects one out of 2N word lines according to an N-bit row address, while the column decoder
circuit selects one out of 2M bit lines according to an M-bit column address. Once a memory cell
or a group of memory cells are selected in this fashion, a data read and/or a data write operation
may be performed on the selected single bit or multiple bits on a particular row. The column
decoder circuit serves the double duties of selecting the particular columns and routing the
corresponding data content in a selected row to the output.
Dynamic RAM
In dynamic RAM (DRAM), the binary data is stored in a parasitic capacitance which discharges
with time. In order to retain the stored data, the capacitor must be charged periodically. This
operation is called dynamic refreshing of DRAM. DRAM can be implemented using one, three,
or four transistors. Figure 3 illustrates the different DRAM architectures.
Operation of DRAM
Semiconductor Memories
Semiconductor memory arrays capable of storing large quantities of digital information are
essential to all digital systems. The amount of memory required in a particular system depends
on the type of application, but, in general, the number of transistors utilized for the information
(data) storage function is much larger than the number of transistors used in logic operations and
for other purposes. The ever-increasing demand for larger data storage capacity has driven the
fabrication technology and memory development towards more compact design rules and,
consequently, toward higher data storage densities. Thus, the maximum realizable data storage
capacity of single-chip semiconductor memory arrays approximately doubles every two years.
On-chip memory arrays have become widely used subsystems in many VLSI circuits, and
commercially available single-chip read/write memory capacity has reached 64 megabits. This
trend toward higher memory density and larger storage capacity will continue to push the
leading edge of digital system design.
The area efficiency of the memory array, i.e., the number of stored data bits per unit area, is one
of the key design criteria that determine the overall storage capacity and, hence, the memory cost
per bit. Another important issue is the memory access time, i.e., the time required to store and/or
retrieve a particular data bit in the memory array. The access time determines the memory speed,
which is an important performance criterion of the memory array. Finally, the static and dynamic
power consumption of the memory array is a significant factor to be considered in the design,
because of the increasing importance of low-power applications. In the following, we will
investigate different types of MOS memory arrays and discuss in detail the issues of area, speed,
and power consumption for each circuit type.
Memory circuits are generally classified according to the type of data storage and the type of
data access. Read-Only Memory (ROM) circuits allow, as the name implies, only the retrieval of
previously stored data and do not permit modifications of the stored information contents during
normal operation. ROMs are non-volatile memories, i.e., the data storage function is not lost
even when the power supply voltage is off. Depending on the type of data storage (data write)
method, ROMs are classified as mask-programmed ROMs, Programmable ROMs (PROM),
Erasable PROMs (EPROM), and Electrically Erasable PROMs (EEPROM).
Figure 1. Overview of semiconductor memory types.
Read-write (R/W) memory circuits, on the other hand, must permit the modification (writing) of
data bits stored in the memory array, as well as their retrieval (reading) on demand. This requires
that the data storage function be volatile, i.e., the stored data are lost when the power supply
voltage is turned off. The read-write memory circuit is commonly called Random Access
Memory (RAM), mostly due to historical reasons. Compared to sequential-access memories such
, as magnetic tapes, any cell in the R/W memory array can be accessed with nearly equal access
time. Based on the operation type of individual data storage cells, RAMs are classified into two
main categories: Static RAMs (SRAM) and Dynamic RAMs (DRAM). Figure 1 shows an
overview of the different memory types and their classifications.
A typical memory array organization is shown in Fig. 2. The data storage structure, or core,
consists of individual memory cells arranged in an array of horizontal rows and vertical
columns. Each cell is capable of storing one bit of binary information. Also, each memory cell
shares a common connection with the other cells in the same row, and another common
connection with the other cells in the same column. In this structure, there are 2N rows, also
called word lines, and 2M columns, also called bit lines. Thus, the total number of memory cells
in this array is 2M x 2N.
Figure 2. Typical random-access memory array organization.
To access a particular memory cell, i.e., a particular data bit in this array, the corresponding bit
line and the corresponding word line must be activated (selected). The row and column selection
operations are accomplished by row and column decoders, respectively. The row decoder circuit
selects one out of 2N word lines according to an N-bit row address, while the column decoder
circuit selects one out of 2M bit lines according to an M-bit column address. Once a memory cell
or a group of memory cells are selected in this fashion, a data read and/or a data write operation
may be performed on the selected single bit or multiple bits on a particular row. The column
decoder circuit serves the double duties of selecting the particular columns and routing the
corresponding data content in a selected row to the output.
Dynamic RAM
In dynamic RAM (DRAM), the binary data is stored in a parasitic capacitance which discharges
with time. In order to retain the stored data, the capacitor must be charged periodically. This
operation is called dynamic refreshing of DRAM. DRAM can be implemented using one, three,
or four transistors. Figure 3 illustrates the different DRAM architectures.
Operation of DRAM
