Dynamic CMOS design: steady-state behavior of dynamic gate circuits, noise considerations in dynamic design, charge sharing, cascading dynamic gates, domino logic, np-CMOS logic, problems in single-phase clocking, two phase non-overlapping clocking scheme

CHAPTER-3: Dynamic CMOS Design
3.1 Steady-state behavior of dynamic gate circuits

3.1.1 H
3.2 Noise consideration in dynamic design

3.2.1 S
3.2.2 M
3.3 Charge Sharing
3.3.1 Gt
3.3.2 V
3.4 Cascading dynamic gates
3.4.1 Design Styles
3.4.1.1 Field Programmable Gate Array Design
3.4.1.2 Gate Array Design
3.4.1.3 Standard Cell-based Design
3.4.1.4 Full-custom Design
3.4.1.5 Semi-custom Design
3.4.2 Packaging
3.4.2.1 Type of IC Packages
3.4.2.2 Types of Packages Based on Package Material
3.4.2.3 Package Modelling
3.5 Domino logic
3.5.1 Design hierarchy-structural,
3.5.2 Levels of abstraction
3.5.2.1 Regularity, Modularity and Locality
3.6 Np-CMOS logic
3.6.1 CMOS Integrated Circuit
3.6.1.1 Issues with ICs at the DSM Level
3.6.2 Digital Logic Design
3.6.2.1 Design
3.6.2.2 Operation
3.6.2.3 Transient and VTC Characteristics
3.6.3 Propagation delay definitions,
3.6.3.1 Critical path
3.6.3.2 Worst case timing analysis, and Sheet resistance

, UNIT-3
1. Dynamic logic
In static logic families the pull up and pull down networks operate concurrently. Dynamic logic
on the other hand uses a sequence of pre-charge and conditional evaluation phases governed by
the clock to realize complex logic functions.




Figure 1 Dynamic logic

A dynamic logic block is shown in Fig. 1. Both forms of Fig.1 can be used. In our analysis we
will concentrate on Fig.1 n-logic network. The operation of the pulldown network (PDN) can be
divided into two major phases. The precharge and the evaluation phase. In what mode the circuit
is operating is determined by the signal φ, the “clock” signal. Let us take an example of either
network: