2 UNIT-II Interconnect Parameters
2.1 An Overview Of The VLSI Interconnect Problem
2.1.1 Interconnect Scaling Problem
2.1.2 Interconnect Geometry
2.1.3 Interconnect Modeling
2.2 Resistance
2.3 Capacitance
2.4 Inductance
2.4.1 Skin effect and its influence
2.5 Lumped RC Model
2.6 Distributed RC Model
2.7 Transmission Line Model
2.7.1 Simulation Model
2.8 RC delay Model
2.8.1 Transient Response
2.8.2 Elmore Delay Model
2.9 Linear Delay Model
2.9.1 Logic Effort
2.9.2 Parasitic Delay
2.10 Logic Effort of Path
2.10.1 Delay in Multistage Logic Networks
,2.1 AN OVERVIEW OF THE VLSI INTERCONNECT PROBLEM
Very-large-scale integration (VLSI) industry has tremendous growth over several decades due to
scaling the devices and interconnect by fulfilling the demand and requirement. According to
Moore’s law, the feature size of integrated circuits (ICs) reduces and the total number of
transistors rapidly increases, which gets double on a single silicon chip after every 2 years. The
designer is continuously following Moore’s concept; however, the complexity of the electronics
system increases with the innovations and demand for high-speed operations. In the early stage
of the ICs industry, the speed of ICs depended on the gate delay instead of the interconnect
delay. Consequently, interconnect is considered as a second-class citizen that appears only at the
time of any high-performance task or any special computational task. As the technology has
moved forward from deep submicron to nanotechnology, several reductions have been
demonstrated such as the size of the metal oxide semiconductor (MOS) transistor, silicon area,
and power consumption. In order to scale down the technology and operate at high frequency,
the impact of interconnect needs to be considered that primarily dominates the performance of
overall on-chip ICs. Therefore, several materials have been used as an interconnect application
such as aluminum (Al), gold (Au), silver (Ag), and copper (Cu) that have their own limitations
over technology scaling.
2.1.1 Interconnect Scaling Problem
In a typical CMOS VLSI technology, the area occupied by the active device is approximately
10%, while it is 6–10 times more for interconnects. Consequently, the importance of
interconnects achieved major attention as the device density increased and the feature size scaled
down. In the early stages of the ICs industry, Al was preferred as interconnect metal because of
its low resistivity, good adherence to silicon (Si), patternability, and ease of deposition. In
addition, it causes negligible contamination with undesirable impurities in the ICs, and it is
easily available as low-cost material in the earth. However, despite its several advantages, it
tends to have several reliability issues due to electromigration and contact failure effect that
mainly has a major impact on the interconnect performance. Electromigration is the result of the
movement of atoms from one place to another that is caused by the gradual movement of ions in
the conductor. Later, Ag and Au were also investigated for interconnect application, but due to
higher electromigration and quick diffusion into silicon during fabrication the use of Al, Au, and
Ag materials was restricted. In the late 1990s, Cu changed the silicon industry as it provided
better reliability, lower resistivity, higher melting points, higher current density, and ten times
more resistance to electromigration as compared to the above-mentioned materials. The higher
melting point of Cu provides improved thermal stability due to several advantages of Cu that
turn into preferred interconnect material for deep submicron technology. As the VLSI
technology is further scaled down, the performance of interconnect is facing serious challenges,
especially at global signals. Demand for higher operating speed and frequency led to a gradual
increase in the resistivity of interconnect due to electron surface and grain boundary scattering.
As the dimensions are reduced rapidly, it becomes comparable to mean free path (MFP) of an
electron (∼40 nm at room temperature in a Cu), that results in scattering from the interface that
cannot be ignored due to surface scattering, and hence the resistivity of copper increases rapidly.
, Another effect of dimension scaling for Cu interconnect is the increase in current density with
technology scaled down. The per unit length (p.u.l.) of interconnect parasitics increases, which
causes the degradation of interconnect performance and leads to higher propagation delay and
more power dissipation. The rise in power dissipation also causes an increase in heating that
results in electromigration. As these limitations of Cu interconnect are technology dependent and
are going to be more and more severe for the future generation of VLSI chips. Therefore, it is
necessary to look forward to an alternative emerging material.
The designer of an electronic circuit has multiple choices in realizing the interconnections
between the various devices that make up the circuit. State-of-the-art processes offer multiple
layers of Aluminum, and at least one layer of polysilicon. Even the heavily doped n+ or p+
layers, typically used for the realization of source and drain regions, can be employed for wiring
purposes. These wires appear in the schematic diagrams of electronic circuits as simple lines
with no apparent impact on the circuit performance. In our discussion on the integrated-circuit
manufacturing process, it became clear that this picture is overly simplistic, and that the wiring
of today’s integrated circuits forms a complex geometry that introduces capacitive, resistive, and
inductive parasitics. All three have multiple effects on the circuit behavior.
1. An increase in propagation delay, or, equivalently, a drop in performance.
2. An impact on the energy dissipation and the power distribution.
3. An introduction of extra noise sources, which affects the reliability of the circuit.
2.1.2 Interconnect (Wire) Geometry:
Figure 2.1 shows a pair of adjacent wires. The wires have width w, length l, thickness t, and
spacing of s from their neighbours and have a dielectric of height h between them and the
conducting layer below. The sum of width and spacing is called the wire pitch. The thickness to
width ratio t/w is called the aspect ratio. Early CMOS processes had a single metal layer and
until the early 1990s only two or three layers were available, but with advances in chemical-
mechanical polishing it became far more practical to manufacture many metal layers. aluminum
(Al) wires used in older processes gave way to copper (Cu) around the 180 or 130 nm node to
reduce resistance. Soon after, manufacturers began replacing the SiO2 insulator between wires
with a succession of materials with lower dielectric constants (low-k) to reduce capacitance. A
65 nm process typically has 8–10 metal layers and the layer count has been increasing at a rate
of about one layer every process generation or two.
FIGURE 2.1 Interconnect geometry
2.1 An Overview Of The VLSI Interconnect Problem
2.1.1 Interconnect Scaling Problem
2.1.2 Interconnect Geometry
2.1.3 Interconnect Modeling
2.2 Resistance
2.3 Capacitance
2.4 Inductance
2.4.1 Skin effect and its influence
2.5 Lumped RC Model
2.6 Distributed RC Model
2.7 Transmission Line Model
2.7.1 Simulation Model
2.8 RC delay Model
2.8.1 Transient Response
2.8.2 Elmore Delay Model
2.9 Linear Delay Model
2.9.1 Logic Effort
2.9.2 Parasitic Delay
2.10 Logic Effort of Path
2.10.1 Delay in Multistage Logic Networks
,2.1 AN OVERVIEW OF THE VLSI INTERCONNECT PROBLEM
Very-large-scale integration (VLSI) industry has tremendous growth over several decades due to
scaling the devices and interconnect by fulfilling the demand and requirement. According to
Moore’s law, the feature size of integrated circuits (ICs) reduces and the total number of
transistors rapidly increases, which gets double on a single silicon chip after every 2 years. The
designer is continuously following Moore’s concept; however, the complexity of the electronics
system increases with the innovations and demand for high-speed operations. In the early stage
of the ICs industry, the speed of ICs depended on the gate delay instead of the interconnect
delay. Consequently, interconnect is considered as a second-class citizen that appears only at the
time of any high-performance task or any special computational task. As the technology has
moved forward from deep submicron to nanotechnology, several reductions have been
demonstrated such as the size of the metal oxide semiconductor (MOS) transistor, silicon area,
and power consumption. In order to scale down the technology and operate at high frequency,
the impact of interconnect needs to be considered that primarily dominates the performance of
overall on-chip ICs. Therefore, several materials have been used as an interconnect application
such as aluminum (Al), gold (Au), silver (Ag), and copper (Cu) that have their own limitations
over technology scaling.
2.1.1 Interconnect Scaling Problem
In a typical CMOS VLSI technology, the area occupied by the active device is approximately
10%, while it is 6–10 times more for interconnects. Consequently, the importance of
interconnects achieved major attention as the device density increased and the feature size scaled
down. In the early stages of the ICs industry, Al was preferred as interconnect metal because of
its low resistivity, good adherence to silicon (Si), patternability, and ease of deposition. In
addition, it causes negligible contamination with undesirable impurities in the ICs, and it is
easily available as low-cost material in the earth. However, despite its several advantages, it
tends to have several reliability issues due to electromigration and contact failure effect that
mainly has a major impact on the interconnect performance. Electromigration is the result of the
movement of atoms from one place to another that is caused by the gradual movement of ions in
the conductor. Later, Ag and Au were also investigated for interconnect application, but due to
higher electromigration and quick diffusion into silicon during fabrication the use of Al, Au, and
Ag materials was restricted. In the late 1990s, Cu changed the silicon industry as it provided
better reliability, lower resistivity, higher melting points, higher current density, and ten times
more resistance to electromigration as compared to the above-mentioned materials. The higher
melting point of Cu provides improved thermal stability due to several advantages of Cu that
turn into preferred interconnect material for deep submicron technology. As the VLSI
technology is further scaled down, the performance of interconnect is facing serious challenges,
especially at global signals. Demand for higher operating speed and frequency led to a gradual
increase in the resistivity of interconnect due to electron surface and grain boundary scattering.
As the dimensions are reduced rapidly, it becomes comparable to mean free path (MFP) of an
electron (∼40 nm at room temperature in a Cu), that results in scattering from the interface that
cannot be ignored due to surface scattering, and hence the resistivity of copper increases rapidly.
, Another effect of dimension scaling for Cu interconnect is the increase in current density with
technology scaled down. The per unit length (p.u.l.) of interconnect parasitics increases, which
causes the degradation of interconnect performance and leads to higher propagation delay and
more power dissipation. The rise in power dissipation also causes an increase in heating that
results in electromigration. As these limitations of Cu interconnect are technology dependent and
are going to be more and more severe for the future generation of VLSI chips. Therefore, it is
necessary to look forward to an alternative emerging material.
The designer of an electronic circuit has multiple choices in realizing the interconnections
between the various devices that make up the circuit. State-of-the-art processes offer multiple
layers of Aluminum, and at least one layer of polysilicon. Even the heavily doped n+ or p+
layers, typically used for the realization of source and drain regions, can be employed for wiring
purposes. These wires appear in the schematic diagrams of electronic circuits as simple lines
with no apparent impact on the circuit performance. In our discussion on the integrated-circuit
manufacturing process, it became clear that this picture is overly simplistic, and that the wiring
of today’s integrated circuits forms a complex geometry that introduces capacitive, resistive, and
inductive parasitics. All three have multiple effects on the circuit behavior.
1. An increase in propagation delay, or, equivalently, a drop in performance.
2. An impact on the energy dissipation and the power distribution.
3. An introduction of extra noise sources, which affects the reliability of the circuit.
2.1.2 Interconnect (Wire) Geometry:
Figure 2.1 shows a pair of adjacent wires. The wires have width w, length l, thickness t, and
spacing of s from their neighbours and have a dielectric of height h between them and the
conducting layer below. The sum of width and spacing is called the wire pitch. The thickness to
width ratio t/w is called the aspect ratio. Early CMOS processes had a single metal layer and
until the early 1990s only two or three layers were available, but with advances in chemical-
mechanical polishing it became far more practical to manufacture many metal layers. aluminum
(Al) wires used in older processes gave way to copper (Cu) around the 180 or 130 nm node to
reduce resistance. Soon after, manufacturers began replacing the SiO2 insulator between wires
with a succession of materials with lower dielectric constants (low-k) to reduce capacitance. A
65 nm process typically has 8–10 metal layers and the layer count has been increasing at a rate
of about one layer every process generation or two.
FIGURE 2.1 Interconnect geometry
