FETs – Voltage controlled current source
JFET DE-MOSFET E-MOSFET
Mode: Depletion Mode: Depletion / Enhancement Mode: Enhancement
Gate
No voltage on Gate: open channel No voltage on Gate: open channel No voltage on Gate: closed channel
Gate
𝑉𝐺𝑆 > 𝑉𝐷𝑆 : enhancement not possible 𝑉𝐺𝑆 > 𝑉𝐷𝑆 : enhances the channel width 𝑉𝐺𝑆 > 𝑉𝐷𝑆 : enhances the channel width
Gate
𝑉𝐺𝑆 < 𝑉𝐷𝑆 : depletes the channel width 𝑉𝐺𝑆 < 𝑉𝐷𝑆 : depletes the channel width 𝑉𝐺𝑆 < 𝑉𝐷𝑆 : depletion not possible
,Keywords
𝐼𝐷𝑆𝑆 Drain-to-Source Saturation Current: Amount of drain current when 𝑉𝐺𝑆 = 0V
𝑉𝑇 / 𝑉𝐺𝑆(𝑂𝐹𝐹) Threshold Voltage / Gate cut-off Voltage: The gate voltage 𝑉𝐺𝑆 at which a MOSFET starts to conduct
𝑉𝑃 / 𝑉𝐺𝑆(𝑂𝐹𝐹) Pinch-off Voltage / Gate cut-off Voltage: The gate voltage 𝑉𝐺𝑆 at which a JFET starts to conduct
Ohmic Region When 𝐼𝐷 vs 𝑉𝐺𝑆 is linear, which acts as resistance.
Pinch-off Voltage After Ohmic region, when VGS reaches saturation, and ID hardly increases (almost none)
𝑉𝐷𝑆 (at pinch-off) = 𝑉𝐺𝑆 − 𝑉𝑇
Saturation Region Region in which the 𝐼𝐷 hardly increases
DC-Biasing Combining AC circuit with DC-Source to create offset for FET
JFET DE-MOSFET E-MOSFET
Basic connection of JFET Basic connection of DE-MOSFET Basic connection of E-MOSFET (notice extra 𝑅)
Output (/drain) characteristics JFET Output (/drain) characteristics DE-MOSFET Output (/drain) characteristics E-MOSFET
Transfer characteristic JFET Transfer characteristic DE-MOSFET Transfer characteristic E-MOSFET
Q = Quiescent
If in saturation:
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − ) 𝐼𝐷 = 𝐾(𝑉𝐺𝑆 − 𝑉𝑇 )2 𝐼𝐷 = 𝐾(𝑉𝐺𝑆 − 𝑉𝑇 )2
𝑉𝑃
∆𝐼𝐷 √𝐼𝐷𝑆𝑆 ∆𝐼𝐷 ∆𝐼𝐷
𝑔𝑚 = = −2 × √𝐼𝐷 𝑔𝑚 = 𝑔𝑚 =
∆𝑉𝐺𝑆 𝑉𝑃 ∆𝑉𝐺𝑆 ∆𝑉𝐺𝑆
, Calculation with a FET small-signal equivalent circuit
↓ Basic models ↓
↓ Basic models with values ↓
𝑔𝑚 = 2 mS (micro Siemens)
Assumption: 1: Input AC Frequency >>> C/Rg (large input frequency)
2: 𝑣𝑖 is an ideal Voltage Source → 𝑅𝑖𝑛𝑡𝑒𝑟𝑛𝑎𝑙 = ∞ (infinite)
Result: 1: C is short circuited (can be removed from drawing on right)
2: 𝑣𝑔𝑠 = 𝑣𝑔 − 𝑣𝑠
𝑣𝑔𝑠 = 𝑣𝑔 − 0𝑉 = 𝑣𝑖
𝑣𝑔𝑠 = 𝑣𝑖
Replacement Resistance can be calculated, using rd parallel to RD
𝑅𝑋 = 𝑟𝑑 // 𝑅𝐷
Since rd >>> RD, rd can also be ignored for easy calculation purposes. It could be said that: 𝑅𝑋 ≈ 𝑅𝐷
If this is not the case:
𝑟𝑑 × 𝑅𝐷 100𝑘 × 2𝑘
𝑅𝑋 = = = 1,96𝑘
𝑟𝑑 + 𝑅𝐷 100𝑘 + 2𝑘
To calculate the gain: 𝑣𝑜 = −𝑔𝑚 𝑣𝑔𝑠 × 𝑅𝑋
Notice: negative number, due to reversed polarity.
Since vgs = vi: 𝑣𝑜 = −𝑔𝑚 𝑣𝑖 × 𝑅𝑋
𝑣𝑜
So: = −𝑔𝑚 × 𝑅𝑋 = −2 × 10−3 × 2 × 103 = −4,0
𝑣𝑖
Or exact: = −2 × 10−3 × 1,96 × 103 = −3,9
Negative number results in phase rotation of 180◦
JFET DE-MOSFET E-MOSFET
Mode: Depletion Mode: Depletion / Enhancement Mode: Enhancement
Gate
No voltage on Gate: open channel No voltage on Gate: open channel No voltage on Gate: closed channel
Gate
𝑉𝐺𝑆 > 𝑉𝐷𝑆 : enhancement not possible 𝑉𝐺𝑆 > 𝑉𝐷𝑆 : enhances the channel width 𝑉𝐺𝑆 > 𝑉𝐷𝑆 : enhances the channel width
Gate
𝑉𝐺𝑆 < 𝑉𝐷𝑆 : depletes the channel width 𝑉𝐺𝑆 < 𝑉𝐷𝑆 : depletes the channel width 𝑉𝐺𝑆 < 𝑉𝐷𝑆 : depletion not possible
,Keywords
𝐼𝐷𝑆𝑆 Drain-to-Source Saturation Current: Amount of drain current when 𝑉𝐺𝑆 = 0V
𝑉𝑇 / 𝑉𝐺𝑆(𝑂𝐹𝐹) Threshold Voltage / Gate cut-off Voltage: The gate voltage 𝑉𝐺𝑆 at which a MOSFET starts to conduct
𝑉𝑃 / 𝑉𝐺𝑆(𝑂𝐹𝐹) Pinch-off Voltage / Gate cut-off Voltage: The gate voltage 𝑉𝐺𝑆 at which a JFET starts to conduct
Ohmic Region When 𝐼𝐷 vs 𝑉𝐺𝑆 is linear, which acts as resistance.
Pinch-off Voltage After Ohmic region, when VGS reaches saturation, and ID hardly increases (almost none)
𝑉𝐷𝑆 (at pinch-off) = 𝑉𝐺𝑆 − 𝑉𝑇
Saturation Region Region in which the 𝐼𝐷 hardly increases
DC-Biasing Combining AC circuit with DC-Source to create offset for FET
JFET DE-MOSFET E-MOSFET
Basic connection of JFET Basic connection of DE-MOSFET Basic connection of E-MOSFET (notice extra 𝑅)
Output (/drain) characteristics JFET Output (/drain) characteristics DE-MOSFET Output (/drain) characteristics E-MOSFET
Transfer characteristic JFET Transfer characteristic DE-MOSFET Transfer characteristic E-MOSFET
Q = Quiescent
If in saturation:
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − ) 𝐼𝐷 = 𝐾(𝑉𝐺𝑆 − 𝑉𝑇 )2 𝐼𝐷 = 𝐾(𝑉𝐺𝑆 − 𝑉𝑇 )2
𝑉𝑃
∆𝐼𝐷 √𝐼𝐷𝑆𝑆 ∆𝐼𝐷 ∆𝐼𝐷
𝑔𝑚 = = −2 × √𝐼𝐷 𝑔𝑚 = 𝑔𝑚 =
∆𝑉𝐺𝑆 𝑉𝑃 ∆𝑉𝐺𝑆 ∆𝑉𝐺𝑆
, Calculation with a FET small-signal equivalent circuit
↓ Basic models ↓
↓ Basic models with values ↓
𝑔𝑚 = 2 mS (micro Siemens)
Assumption: 1: Input AC Frequency >>> C/Rg (large input frequency)
2: 𝑣𝑖 is an ideal Voltage Source → 𝑅𝑖𝑛𝑡𝑒𝑟𝑛𝑎𝑙 = ∞ (infinite)
Result: 1: C is short circuited (can be removed from drawing on right)
2: 𝑣𝑔𝑠 = 𝑣𝑔 − 𝑣𝑠
𝑣𝑔𝑠 = 𝑣𝑔 − 0𝑉 = 𝑣𝑖
𝑣𝑔𝑠 = 𝑣𝑖
Replacement Resistance can be calculated, using rd parallel to RD
𝑅𝑋 = 𝑟𝑑 // 𝑅𝐷
Since rd >>> RD, rd can also be ignored for easy calculation purposes. It could be said that: 𝑅𝑋 ≈ 𝑅𝐷
If this is not the case:
𝑟𝑑 × 𝑅𝐷 100𝑘 × 2𝑘
𝑅𝑋 = = = 1,96𝑘
𝑟𝑑 + 𝑅𝐷 100𝑘 + 2𝑘
To calculate the gain: 𝑣𝑜 = −𝑔𝑚 𝑣𝑔𝑠 × 𝑅𝑋
Notice: negative number, due to reversed polarity.
Since vgs = vi: 𝑣𝑜 = −𝑔𝑚 𝑣𝑖 × 𝑅𝑋
𝑣𝑜
So: = −𝑔𝑚 × 𝑅𝑋 = −2 × 10−3 × 2 × 103 = −4,0
𝑣𝑖
Or exact: = −2 × 10−3 × 1,96 × 103 = −3,9
Negative number results in phase rotation of 180◦
