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Counters
Difference between Async and sync counters
Modulus
Ripple/Asynchronous Counters
Up Counter
Down Counter
Up/Down Counter
Decoding Gates
Problems
Synchronous Counters
2-bit Synchronous Up Counter
3-bit Synchronous Up Counter
4-bit Synchronous Up Counter
Up/Down Counter
Lock-Out
IC 7490
BCD Decade (8421) Counter
Symmetrical Bi-quinary Divide by Ten Counter
Divide by Two and Divide by Five Counter
Ring Counter
Johnson or Twisting Ring or Switch Tail Counter
Difference between Async and sync counters
Async Counters Sync Counters
O/p of first flip flop drives clock for the next flip
No connection between flip flop and clock input
flop
All FFs are not clocked simultaneously All FFs are clocked simultaneously
Logic circuit is very simple even for more no. Complex logic circuit as number of states
of states increases
Main drawback is the low speed due to There is no problem of propagation delay hence
propagation delay they are preferred when no. of FFs increases
Counters 1
, Modulus
Total number of counts or stable states a counter can indicate is called modulus.
Number
Count = Remainder of [ ] in binary
2n
where n = Number of counter bits
Ripple/Asynchronous Counters
Up Counter
1
fmax =
n ∗ tpd
FCLK
F requency at QA =
2
QA FCLK
F requency at QB = =
2 4
FCLK
...F =
2n
Counters 2
Counters
Difference between Async and sync counters
Modulus
Ripple/Asynchronous Counters
Up Counter
Down Counter
Up/Down Counter
Decoding Gates
Problems
Synchronous Counters
2-bit Synchronous Up Counter
3-bit Synchronous Up Counter
4-bit Synchronous Up Counter
Up/Down Counter
Lock-Out
IC 7490
BCD Decade (8421) Counter
Symmetrical Bi-quinary Divide by Ten Counter
Divide by Two and Divide by Five Counter
Ring Counter
Johnson or Twisting Ring or Switch Tail Counter
Difference between Async and sync counters
Async Counters Sync Counters
O/p of first flip flop drives clock for the next flip
No connection between flip flop and clock input
flop
All FFs are not clocked simultaneously All FFs are clocked simultaneously
Logic circuit is very simple even for more no. Complex logic circuit as number of states
of states increases
Main drawback is the low speed due to There is no problem of propagation delay hence
propagation delay they are preferred when no. of FFs increases
Counters 1
, Modulus
Total number of counts or stable states a counter can indicate is called modulus.
Number
Count = Remainder of [ ] in binary
2n
where n = Number of counter bits
Ripple/Asynchronous Counters
Up Counter
1
fmax =
n ∗ tpd
FCLK
F requency at QA =
2
QA FCLK
F requency at QB = =
2 4
FCLK
...F =
2n
Counters 2