Programmable Logic Devices
Fixed function IC Approach V/S ASIC Approach V/S PLD Approach
PLD Classification
Programmable Read Only Memory PROM
AND Matrix
OR Matrix
Inverting and Non Inverting Matrix
Programmable Logic Array PLA
Input Buffers
Output Buffer
Output through Flip Flops
Programmable Array Logic PAL
PROM v/s PLA v/s PAL
Field Programmable Gate Array FPGA
LUT
The Logic Block
The Logic Element
Fixed function IC Approach V/S ASIC
Approach V/S PLD Approach
Comparison Fixed Function IC
ASIC Approach PLD Approach
Parameter Approach
Development
Low High Low
Cost
Space Required Large Minimum Less
Power Required Large Less Less
Less compared to
Reliability other two Highest High
approaches
Programmable Logic Devices 1
, Comparison Fixed Function IC
ASIC Approach PLD Approach
Parameter Approach
Specialized testing
methods are required
Circuit Testing Easy Easy
which may increase
cost and effort
Design
Less No More
Flexibility
Possible with May be possible without any
Modification in change in circuit circuit or component changes
No
design and/or change in but only by reconfiguring the
components device
Lack of security
Design Security i.e. circuit can High High
easily be copied
Design Time Less More Less
PLD Classification
1. PROM: Programmable Read Only Memory
2. PLA: Programmable Logic Array
3. PAL: Programmable Array Logic
4. FPGA: Field Programmable Gate Array
5. CPLD: Complex Programmable Logic Design
Programmable Read Only Memory PROM
Programmable Logic Devices 2
, Each bit combination of input variables is called address. The address specified in
binary numbers denotes one of the minterms of n variables. The number of distinct
addresses possible with n-input variables is 2n .
Each bit combination that comes out of the output lines is called a word. The number of
bits per word is equal to m. An output word can be selected by a unique address and
since there are 2n distinct addresses, there 2n distinct words in the PROM.
AND Matrix
Programmable Logic Devices 3
Fixed function IC Approach V/S ASIC Approach V/S PLD Approach
PLD Classification
Programmable Read Only Memory PROM
AND Matrix
OR Matrix
Inverting and Non Inverting Matrix
Programmable Logic Array PLA
Input Buffers
Output Buffer
Output through Flip Flops
Programmable Array Logic PAL
PROM v/s PLA v/s PAL
Field Programmable Gate Array FPGA
LUT
The Logic Block
The Logic Element
Fixed function IC Approach V/S ASIC
Approach V/S PLD Approach
Comparison Fixed Function IC
ASIC Approach PLD Approach
Parameter Approach
Development
Low High Low
Cost
Space Required Large Minimum Less
Power Required Large Less Less
Less compared to
Reliability other two Highest High
approaches
Programmable Logic Devices 1
, Comparison Fixed Function IC
ASIC Approach PLD Approach
Parameter Approach
Specialized testing
methods are required
Circuit Testing Easy Easy
which may increase
cost and effort
Design
Less No More
Flexibility
Possible with May be possible without any
Modification in change in circuit circuit or component changes
No
design and/or change in but only by reconfiguring the
components device
Lack of security
Design Security i.e. circuit can High High
easily be copied
Design Time Less More Less
PLD Classification
1. PROM: Programmable Read Only Memory
2. PLA: Programmable Logic Array
3. PAL: Programmable Array Logic
4. FPGA: Field Programmable Gate Array
5. CPLD: Complex Programmable Logic Design
Programmable Read Only Memory PROM
Programmable Logic Devices 2
, Each bit combination of input variables is called address. The address specified in
binary numbers denotes one of the minterms of n variables. The number of distinct
addresses possible with n-input variables is 2n .
Each bit combination that comes out of the output lines is called a word. The number of
bits per word is equal to m. An output word can be selected by a unique address and
since there are 2n distinct addresses, there 2n distinct words in the PROM.
AND Matrix
Programmable Logic Devices 3
