Cos2621 assignment 1 2022
Question 1 [10]
(a) The following table reflects the contents of a part of memory in a one‐address machine
with an accumulator:
Address Contents
00 20
20 30
30 40
40 50
50 60
60 70
What values do the following instructions load into the accumulator?
LOAD IMMEDIATE 20: Immediate addressing. The value to be used forms part of the
instruction. In this instance, the value 20 will be loaded into the accumulator.
LOAD DIRECT 20: Direct addressing. The instruction contains the address where the value is
to found. Address 20 contains the value 30, thus the value 30 will be loaded into the
accumulator.
LOAD INDIRECT 20: Indirect addressing. The instruction contains the address where the
address of the value to be used, is to be found. Address 20 contains the address of the value to
be used, ie address 30. Address 30 contains 40, thus the value 40 will be loaded into the
Accumulator.
b) Give examples of Intel x86 instructions in which the following addressing modes are
used:
Immediate addressing mov al,3
Direct addressing mov al,[temp]
Stack addressing push ax (pop ax)
Indexed addressing mov al,[si] (mov [di],al)
Base‐addressing mov al,[bp]
, Register indirect addressing mov al,[bp] (mov al,[si], mov [di],al)
Question 2 [11]
(a) Briefly discuss the concepts of (i) error correcting‐codes and (ii) error‐detecting codes.
(i) Error‐correcting codes are used when an error is detected in the error‐detecting
process. The number of bit errors in a word plays an important role. The
Hamming code is often used for error‐correction. Parity bits are used in this
process. By a process of elimination (see Stallings , fig 5.8) errors can be
corrected. For a detailed description of this process, refer to Stallings, 9th
edition, p 193)
(ii) Error‐detecting codes use parity bits to detect hardware failures and soft errors.
b) What is the distinction between spatial locality and temporal locality?
Spatial locality refers to the tendency of execution to involve a number of clustered
memory locations. A program also tends to access data locations sequentially.
Temporal locality refers to the tendency for a processor to access memory locations
that have been used recently, eg when a loop is executed, the processor executes the
same instructions repeatedly.
c) Briefly describe the cache organisation of the Pentium 4.
- L1 instruction cache (on-chip): 12K in size and holds micro-operations. Sits between the
instruction decode logic and the execution core.
- L1 data cache (on-chip): 16Kb, 4-way set-associative organisation. Uses a writeback
policy.
- L2 cache of 256Kb: Feeds both L1 data and instruction caches. Its organisation is 8- way
set-associative.
- L3 cache: on-chip (8-way set-associative).
Memory subsystem: This unit contains both the L2 and L3 caches and the system bus. The
bus is used to access main memory when the L1 and L2 caches have a cache miss.
Question 3 [9]
Question 1 [10]
(a) The following table reflects the contents of a part of memory in a one‐address machine
with an accumulator:
Address Contents
00 20
20 30
30 40
40 50
50 60
60 70
What values do the following instructions load into the accumulator?
LOAD IMMEDIATE 20: Immediate addressing. The value to be used forms part of the
instruction. In this instance, the value 20 will be loaded into the accumulator.
LOAD DIRECT 20: Direct addressing. The instruction contains the address where the value is
to found. Address 20 contains the value 30, thus the value 30 will be loaded into the
accumulator.
LOAD INDIRECT 20: Indirect addressing. The instruction contains the address where the
address of the value to be used, is to be found. Address 20 contains the address of the value to
be used, ie address 30. Address 30 contains 40, thus the value 40 will be loaded into the
Accumulator.
b) Give examples of Intel x86 instructions in which the following addressing modes are
used:
Immediate addressing mov al,3
Direct addressing mov al,[temp]
Stack addressing push ax (pop ax)
Indexed addressing mov al,[si] (mov [di],al)
Base‐addressing mov al,[bp]
, Register indirect addressing mov al,[bp] (mov al,[si], mov [di],al)
Question 2 [11]
(a) Briefly discuss the concepts of (i) error correcting‐codes and (ii) error‐detecting codes.
(i) Error‐correcting codes are used when an error is detected in the error‐detecting
process. The number of bit errors in a word plays an important role. The
Hamming code is often used for error‐correction. Parity bits are used in this
process. By a process of elimination (see Stallings , fig 5.8) errors can be
corrected. For a detailed description of this process, refer to Stallings, 9th
edition, p 193)
(ii) Error‐detecting codes use parity bits to detect hardware failures and soft errors.
b) What is the distinction between spatial locality and temporal locality?
Spatial locality refers to the tendency of execution to involve a number of clustered
memory locations. A program also tends to access data locations sequentially.
Temporal locality refers to the tendency for a processor to access memory locations
that have been used recently, eg when a loop is executed, the processor executes the
same instructions repeatedly.
c) Briefly describe the cache organisation of the Pentium 4.
- L1 instruction cache (on-chip): 12K in size and holds micro-operations. Sits between the
instruction decode logic and the execution core.
- L1 data cache (on-chip): 16Kb, 4-way set-associative organisation. Uses a writeback
policy.
- L2 cache of 256Kb: Feeds both L1 data and instruction caches. Its organisation is 8- way
set-associative.
- L3 cache: on-chip (8-way set-associative).
Memory subsystem: This unit contains both the L2 and L3 caches and the system bus. The
bus is used to access main memory when the L1 and L2 caches have a cache miss.
Question 3 [9]
