Signal_Processing_and_Embedded_Systems_Syllabus_M._Tech._.pdf

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KANNUR UNIVERSITY




Faculty of Engineering
Curriculum, Scheme of Examinations and Syllabi for M. Tech. Degree
Program with effect from Academic Year 2012-2013



Electronics & Communication Engineering


M. Tech.
in

Signal Processing and Embedded Systems

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FIRST SEMESTER


University
Hours/Week Sessional
Code Subject Examination Credit
Marks
L T P Hrs Marks
Linear Algebra for Signal
SPE 101 3 - - 50 3 100 3
Processing
Random Processes and
SPE 102 3 - - 50 3 100 3
Applications
Design using Embedded
SPE 103 3 - - 50 3 100 3
Processers
SPE 104 DSP and Applications 3 - - 50 3 100 3
SPE 105 Elective I 3 - - 50 3 100 3
SPE 106 Elective II 3 - - 50 3 100 3
SPE 107 (P) Digital Signal Processing Lab - - 2 50 3 100 2
SPE 108 (P) Seminar - - 2 50 - - 2
TOTAL 18 4 400 700 22


ELECTIVE-I
SPE 105 (A) Digital VLSI Design
SPE 105 (B) DSP Processors and Architecture
SPE 105 (C) High Speed Digital Design
SPE 105 (D) Multi-rate Signal Processing


ELECTIVE II
SPE 106 (A) Biomedical Signal Processing and Systems
SPE 106 (B) Advanced Digital System Design
SPE 106 (C) Adaptive Signal Processing
SPE 106 (D) Analog Integrated Circuit Design

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SECOND SEMESTER


University
Hours/Week Sessional
Code Subject Examination Credit
Marks
L T P Hrs Marks
SPE 201 Digital Image Processing 3 - - 50 3 100 3
SPE 202 Wavelet Theory 3 - - 50 3 100 3
SPE 203 Embedded Systems 3 - - 50 3 100 3
SPE 204 Elective III 3 - - 50 3 100 3
SPE 205 Elective IV 3 - - 50 3 100 3
SPE206 Elective V 3 - - 50 3 100 3
SPE 207 (P) VLSI & Embedded Systems Lab - - 2 50 3 100 2
SPE 208 (P) Term Paper - - 2 50 - - 2
TOTAL 18 4 400 700 22


ELECTIVE-III
SPE 204 (A) Statistical Signal Processing
SPE 204 (B) CMOS Mixed Signal Circuit Design
SPE 204 (C) Multimedia Systems
SPE 204 (D) ASIC Design


ELECTIVE-IV
SPE 205 (A) Speech Processing
SPE 205 (B) Low Power VLSI Design
SPE 205 (C) Biometric Processing
SPE 205 (D) Introduction to Nano Electronics


ELECTIVE-V
SPE 206 (A) Pattern Recognition and Computer Vision
SPE 206 (B) Research Methodologies
SPE 206 (C) Embedded Networks
SPE 206 (D) VLSI System Design

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THIRD SEMESTER

Code Subject Hrs / Week Marks Credits
L T P Internal University Total
Guide Evaluation Thesis Viva
Committee
SPE 301 (P) Thesis 22 200 200 -- -- 400 8
Preliminary
Total 22 200 200 400 8



THESIS PRELIMINARY

This shall comprise of two seminars and submission of an interim thesis report. This report
shall be evaluated by the evaluation committee. The fourth semester Thesis- Final shall be an
extension of this work in the same area. The first seminar would highlight the topic,
objectives, methodology and expected results. The first seminar shall be conducted in the first
half of this semester. The second seminar is presentation of the interim thesis report of the
work completed and scope of the work which is to be accomplished in the fourth semester.