Lecture-9
Dynamic RAM chip:
A dynamic RAM (DRAM) comprises storage cells that may be
thought of eclectically as capacitors. There are many thousands of
these capacitors, or storage cells, on a dynamic RAM chip. Each cell
is capable of storing one bit of information. If the capacitor is charged,
one may say the bit stored is logic ‘1’ and if the capacitor is
discharged, the stored bit may be considered logic ‘0’. Therefore,
number of ca
The capacitor that makes this storage cell is not ideal. That is,
charge placed on this capacitor will leak off given enough time. In a
DRAM, the charge on the capacitor represents the stored data.
Therefore, the data stored in the cell can be lost. A more accurate
model of the storage cell is a capacitor in parallel with a resistor.
To keep the stored information in a capacitor cell, DRAM is
refreshed again & again. In a dynamic RAM, the storage cells are
organized in a matrix form. Fig shows, the organization of 16 cells in
a matrix of 4x4, i.e., 4 rows and 4 columns. Each cell in a matrix has
a unique position specified by the intersection of a row & a column.
, Using Row & Column, any cell can be uniquely identified.
External signal lines are used to indicate which storage cell of the
matrix is to be accessed. These lines are called row address lines &
column address lines.
Due to the way in which DRAMs are fabricated, the storage
capacitor is not capable of providing large output current to an
external load. Therefore, a circuit called sense amplifier is placed at
the output of the storage capacitor to increase the output current
drive capability of the cell.
Dynamic RAM chip:
A dynamic RAM (DRAM) comprises storage cells that may be
thought of eclectically as capacitors. There are many thousands of
these capacitors, or storage cells, on a dynamic RAM chip. Each cell
is capable of storing one bit of information. If the capacitor is charged,
one may say the bit stored is logic ‘1’ and if the capacitor is
discharged, the stored bit may be considered logic ‘0’. Therefore,
number of ca
The capacitor that makes this storage cell is not ideal. That is,
charge placed on this capacitor will leak off given enough time. In a
DRAM, the charge on the capacitor represents the stored data.
Therefore, the data stored in the cell can be lost. A more accurate
model of the storage cell is a capacitor in parallel with a resistor.
To keep the stored information in a capacitor cell, DRAM is
refreshed again & again. In a dynamic RAM, the storage cells are
organized in a matrix form. Fig shows, the organization of 16 cells in
a matrix of 4x4, i.e., 4 rows and 4 columns. Each cell in a matrix has
a unique position specified by the intersection of a row & a column.
, Using Row & Column, any cell can be uniquely identified.
External signal lines are used to indicate which storage cell of the
matrix is to be accessed. These lines are called row address lines &
column address lines.
Due to the way in which DRAMs are fabricated, the storage
capacitor is not capable of providing large output current to an
external load. Therefore, a circuit called sense amplifier is placed at
the output of the storage capacitor to increase the output current
drive capability of the cell.
