Module 05: Contact Hours: 10
Semiconductor Memories:
Introduction, Read-Only Memory (ROM) Circuits-4-bit x 4-bit NOR-based ROM array, A 4-
bit x 4-bit NAND-based ROM array, Design of Row and Column Decoders, Static Read-
Write Memory (SRAM) Circuits, Dynamic Read-Write Memory (DRAM) Circuits-Three-
Transistor DRAM Cell, One-Transistor DRAM Cell.
CMOS Testing-Design for Testability:
Introduction, Fault Types and Models, Controllability and Observability, Ad Hoc Testable
Design Techniques, Scan-Based Techniques, Built-In Self-Test (BIST) Techniques, Current
Monitoring IDDQ Test
Semiconductor Memories:
Data storage capacity available on a single integrated circuit grows exponentially being
doubled approximately every two years.
• Capacity of the dynamic read/write memory (DRAM) chip exceeds now 1 Gigabit.
• Data transfer speed of a standard DRAM is at the level of 200Mb/sec/pin.
Semiconductor Memories are classified according to the type of data storage and the type
of data access mechanism into the following two main groups:
Non-volatile Memory (NVM) also known as Read-Only Memory (ROM) which retains
information when the power supply voltage is off. With respect to the data storage
mechanism NVM are divided into the following groups:
o Mask programmed ROM. The required contents of the memory is programmed during
fabrication,
o Programmable ROM (PROM). The required contents are written in a permanent way
by burning out internal interconnections (fuses). It is a one-off procedure.
o Erasable PROM (EPROM). Data is stored as a charge on an isolated gate capacitor
(“floating gate”). Data is removed by exposing the PROM to the ultraviolet light.
o Electrically Erasable PROM (EEPROM) also known as Flash Memory. It is also base
on the concept of the floating gate. The contents can be re-programmed by applying
suitable voltages to the EEPROM pins. The Flash Memories are very important data
storage devices for mobile applications.
Read/Write (R/W) memory, also known as Random Access Memory (RAM). From the
point of view of the data storage mechanism RAM are divided into two main groups:
o Static RAM, where data is retained as long as there is power supply on.
, o Dynamic RAM, where data is stored on capacitors and requires a periodic
refreshment.
Typical organization of a single chip semiconductor memory is shown in Figure
The memory consists of the following basic blocks:
• The array of 1-bit memory cells,
• The row decoder which selects a single word line for a given n-bit row address a[1:n],
• The column decoder which selects a single bit line for a given m-bit column address
b[1:m], and routs a 1-bit data to or from a selected memory cell.
, Read-Only Memory (ROM) Circuits
The read-only memory array can also be seen as a simple combinational Boolean
network which produces a specified output value for each input combination,i.e., for each
address.
Thus, storing binary information at a particular address location can be achieved by
the presence or absence of a data path from the selected row (word line) to the selected
column (bit line), which is equivalent to the presence or absence of a device at that particular
location.
NOR-based ROM
The building block of this ROM is a pseudo-nMOS NOR gate as in Figure.
Unlike in a standard CMOS gate, the pMOS pull-up circuitry is replaced by a
single pMOS with its gate tied up to GND, hence being permanently on acting
as a load resistor.
If none of the nMOS transistors are activated (all Ri being low) then the output
signal C is high.
If any of the nMOS transistors is activated (Ri being high) then the output
signal C is low.
A 4-bit x 4-bit NOR-based ROM array
In the following, we will examine two different implementations for MOS ROM
arrays. Consider first the 4-bit x4-bit memory array shown in Fig. Here, each column consists
of a pseudo-nMOS NOR gate driven by some of the row signals, i.e., the word lines.
Semiconductor Memories:
Introduction, Read-Only Memory (ROM) Circuits-4-bit x 4-bit NOR-based ROM array, A 4-
bit x 4-bit NAND-based ROM array, Design of Row and Column Decoders, Static Read-
Write Memory (SRAM) Circuits, Dynamic Read-Write Memory (DRAM) Circuits-Three-
Transistor DRAM Cell, One-Transistor DRAM Cell.
CMOS Testing-Design for Testability:
Introduction, Fault Types and Models, Controllability and Observability, Ad Hoc Testable
Design Techniques, Scan-Based Techniques, Built-In Self-Test (BIST) Techniques, Current
Monitoring IDDQ Test
Semiconductor Memories:
Data storage capacity available on a single integrated circuit grows exponentially being
doubled approximately every two years.
• Capacity of the dynamic read/write memory (DRAM) chip exceeds now 1 Gigabit.
• Data transfer speed of a standard DRAM is at the level of 200Mb/sec/pin.
Semiconductor Memories are classified according to the type of data storage and the type
of data access mechanism into the following two main groups:
Non-volatile Memory (NVM) also known as Read-Only Memory (ROM) which retains
information when the power supply voltage is off. With respect to the data storage
mechanism NVM are divided into the following groups:
o Mask programmed ROM. The required contents of the memory is programmed during
fabrication,
o Programmable ROM (PROM). The required contents are written in a permanent way
by burning out internal interconnections (fuses). It is a one-off procedure.
o Erasable PROM (EPROM). Data is stored as a charge on an isolated gate capacitor
(“floating gate”). Data is removed by exposing the PROM to the ultraviolet light.
o Electrically Erasable PROM (EEPROM) also known as Flash Memory. It is also base
on the concept of the floating gate. The contents can be re-programmed by applying
suitable voltages to the EEPROM pins. The Flash Memories are very important data
storage devices for mobile applications.
Read/Write (R/W) memory, also known as Random Access Memory (RAM). From the
point of view of the data storage mechanism RAM are divided into two main groups:
o Static RAM, where data is retained as long as there is power supply on.
, o Dynamic RAM, where data is stored on capacitors and requires a periodic
refreshment.
Typical organization of a single chip semiconductor memory is shown in Figure
The memory consists of the following basic blocks:
• The array of 1-bit memory cells,
• The row decoder which selects a single word line for a given n-bit row address a[1:n],
• The column decoder which selects a single bit line for a given m-bit column address
b[1:m], and routs a 1-bit data to or from a selected memory cell.
, Read-Only Memory (ROM) Circuits
The read-only memory array can also be seen as a simple combinational Boolean
network which produces a specified output value for each input combination,i.e., for each
address.
Thus, storing binary information at a particular address location can be achieved by
the presence or absence of a data path from the selected row (word line) to the selected
column (bit line), which is equivalent to the presence or absence of a device at that particular
location.
NOR-based ROM
The building block of this ROM is a pseudo-nMOS NOR gate as in Figure.
Unlike in a standard CMOS gate, the pMOS pull-up circuitry is replaced by a
single pMOS with its gate tied up to GND, hence being permanently on acting
as a load resistor.
If none of the nMOS transistors are activated (all Ri being low) then the output
signal C is high.
If any of the nMOS transistors is activated (Ri being high) then the output
signal C is low.
A 4-bit x 4-bit NOR-based ROM array
In the following, we will examine two different implementations for MOS ROM
arrays. Consider first the 4-bit x4-bit memory array shown in Fig. Here, each column consists
of a pseudo-nMOS NOR gate driven by some of the row signals, i.e., the word lines.
