CSE/EEE 120 Lab 1 Answer Sheet Half Adder, Full Adder, 4-bit Incrementor and Adder

CSE/EEE 120 Lab 1 Answer Sheet Half Adder, Full Adder, 4-bit Incrementor and Adder Name:___Simran Bhalla___________ Instructor/Time:__Tuesday-Thursday (12:00PM1:15PM)___________________ Date:___February 17, 2020_______ Task 1-1: Build and Test the 1-Bit Half-Adder Include a picture of your Quartus circuit here: 1 Please comment on the single biggest issue you were facing when designing the circuit. Answer: The biggest issue I had while designing the circuit was aligning the circuit diagram. I had a little problem with the pins and had to re do that a couple times. Include a picture of your Quartus simulation (timing diagram) here: Answer: Did the circuit behave as expected? If no, what was wrong? Answer: Yes, the circuit behaved as expected. There was no error and the timing diagram worked perfectly, as well. Please comment on the single biggest issue you were facing when simulating the circuit. Answer: The single biggest issue I faced while simulating the circuit was to make sure all the inputs were imported correctly. 2 Task 1-2: Build and Test a 4-Bit Increment Circuit Include a picture of your Quartus circuit here: Answer: Please comment on the single biggest issue you were facing when designing the circuit. Answer: The single biggest issue I was facing while designing the circuit was: aligning and connecting the circuit perfectly.