EEE 120 Lab 1 Answer Sheet (Online) Half Adder, Full Adder, 4-bit Incrementer and Adder

EEE 120 Lab 1 Answer Sheet (Online) Half Adder, Full Adder, 4-bit Incrementer and Adder Name: xxxx Date: 11/3/19 Task 1-1: Build and Test the 1-Bit Half-Adder Include a picture of your Quartus circuit here: Please comment on the single biggest issue you were facing when designing the circuit. a. The biggest issues was remembering to save and compile before trying to run the waveform Include a picture of your Quartus simulation (timing diagram) here: 1 Did the circuit behave as expected? If no, what was wrong? a. Everything preformed as expected Please comment on the single biggest issue you were facing when simulating the circuit. a. I had no issues running the simulation Task 1-2: Build and Test a 4-Bit Increment Circuit Include a picture of your Quartus circuit here: Please comment on the single biggest issue you were facing when designing the circuit. a. I had no issues designing this circuit other than lining everything up Include a picture of your Quartus simulation (timing diagram) here: 2 Did you test all input conditions? a. Yes Were the results as you expected them to be? a. Yes If you performed your own test sequence, which tests did you perform and why? The following table is an example of how to describe your test sequence: Please comment on the single biggest issue you were facing when simulating the circuit. a. My biggest issue was trying to bring the program to the top level so I could load that onto the board Task 1-3: Test the 4-bit Increment Circuit using LEDs on Hardware Include a picture of your Quartus System Message Window here: Include a picture of your Programmer Window here: 3 Was the test on the FPGA board successful? a. Yes the following table shows the tests and why they were preformed