Microelectronics 723
VDD VGG VDD VDD
VO VO VO
V in V in V in
(a) (b) (c)
FIGURE 8.13 NMOS inverters with different types of active loads: (a) saturated enhancement load, (b) linear en-
hancement load, (c) depletion load.
The saturated enhancement load inverter overcomes much of the area disadvantage of the resistive
load inverter. When carrying the same current and having the same pull-down transistor as the resistive
inverter, however, K R is large for the saturated enhancement load inverter, indicating load transistor area
minimization is still possible. This configuration yields a smaller logic swing relative to the resistive load
inverter, however, because the load transistor stops conducting when its VG S = VD S decreases to VT . Thus,
for this inverter, VOH = VD D − VT .
In Fig. 8.13(b), because VG G is greater than VD D + VT , VD S is always smaller than VG S − VT ; thus, the
load always operates in the linear region. This results in a linear enhancement load NMOS inverter. The
high value of VG G also ensures that VG S is always greater than VT , so that the load remains on and VO H pulls
up to VD D . The linear enhancement load configuration, however, requires a load transistor of larger area
relative to the saturated enhancement load inverter, and requires additional chip area for the VG G contact.
In the depletion NMOS load inverter of Fig. 8.13(c), VG S = 0, thus the load device is always on and VO H
pulls all the way to VD D . This configuration overcomes the area disadvantage without incurring a voltage
swing penalty. It is, therefore, the preferred alternative. The performance of the NMOS inverters with the
four different types of loads are graphically compared in Fig. 8.14(a) and Fig. 8.14(b). Both the loadlines
ID VO
5V
VGS
2.5
(a) 0 1 2 3 4V VDS (b) 0 1 2 3 4V V in
DEPLETION LOAD
RESISTIVE LOAD
LINEAR ENH. LOAD
SATURATED ENH. LOAD
FIGURE 8.14 Performance of NMOS inverters with different types of loads: (a) output characteristics and load lines,
(b) voltage transfer characteristics.
Copyright 2005 by Taylor & Francis Group
, 724 Electronics Handbook
and the voltage transfer characteristics were obtained from SPICE simulation. Figure 8.14(a) shows the
loadlines superimposed on the output characteristics of the pull-down transistor, which is the same for the
four inverters. R L is 100 k and each inverter has VDD = 5 V, VOL = 0.2 V and I D max = 48 µA. Note that
VOH falls short of VDD for the saturated enhancement load inverter but not for the others. Figure 8.14(b)
shows the voltage transfer characteristics (VTC) for the four inverters. VOH is again shown to be less than
VDD for the saturated enhancement load. Note, also, that the depletion load VTC more closely approaches
the ideal inverter VTC than any of the others.
The loadlines of Fig. 8.13(a) are easy to generate. Consider, for example the depletion NMOS load. VG S
is fixed at 0 V, so that its output characteristic consists of only the curve for VG S = 0. I D is always the same
for the load and driving transistor, but their VD S add up to VD D . Thus, when VD S is high for one transistor,
it is low for the other. The loadline is obtained by shifting the origin for VD S for the load characteristic to
VD D , reflecting it about the vertical axis through VD D and superimposing it on the V –I characteristics for
the driving inverter.
The voltage transfer characteristics are best generated by computer simulation. Useful insights, however,
can be gained from an analysis yielding the critical voltages VO H , VO L , VI H , VI L , and VO for any specified
Vin . The NMOS currents hold the key to such an analysis. Threshold voltages are different for enhancement
and depletion NMOS transistors, but the drain current equations are the same. The drain current is given
in the linear region and the saturated region, respectively, by
I D = K n 2(VG S − VT )VD S − VD2 S ; VD S ≤ VG S − VT (8.3)
I D = K n (VG S − VT )2 ; VD S ≥ VG S − VT (8.4)
where
VT = threshold
voltage
Kn = µn2C ox wL = transconductance
µn = electron channel mobility
C ox = gate capacitance per unit area
Similar definitions apply to PMOS transistors.
Consider the VTC of Fig. 8.15(a) for a depletion load NMOS inverter. For the region 0 < Vin < VT the
driving transistor is off, so VO H = VD D . At A, Vin is small; thus, for the driving transistor, VD S = VO >
Vin − VT = VG S − VT . For the load VD S = VD D − VO is small. Hence, the driver is saturated and load
VO VO
5V A 5V
4 4
3 B 3
2 2
1 C 1
0 1 2 3 4 5V V in 0 1 2 3 4 5 V V in
REGIONS GEOMETRIC RATIOS
DRIVER OFF, LOAD LINEAR KR = 2
DRIVER SATURATED, LOAD LINEAR KR = 4
(a) DRIVER LINEAR, LOAD SATURATED (b) KR = 8
FIGURE 8.15 Regions of the VTC and VTCs for different geometric ratios for the depletion load NMOS inverters:
(a) depletion load NMOS inverter VTC and its regions, (b) VTCs for different geometric ratios.
Copyright 2005 by Taylor & Francis Group
VDD VGG VDD VDD
VO VO VO
V in V in V in
(a) (b) (c)
FIGURE 8.13 NMOS inverters with different types of active loads: (a) saturated enhancement load, (b) linear en-
hancement load, (c) depletion load.
The saturated enhancement load inverter overcomes much of the area disadvantage of the resistive
load inverter. When carrying the same current and having the same pull-down transistor as the resistive
inverter, however, K R is large for the saturated enhancement load inverter, indicating load transistor area
minimization is still possible. This configuration yields a smaller logic swing relative to the resistive load
inverter, however, because the load transistor stops conducting when its VG S = VD S decreases to VT . Thus,
for this inverter, VOH = VD D − VT .
In Fig. 8.13(b), because VG G is greater than VD D + VT , VD S is always smaller than VG S − VT ; thus, the
load always operates in the linear region. This results in a linear enhancement load NMOS inverter. The
high value of VG G also ensures that VG S is always greater than VT , so that the load remains on and VO H pulls
up to VD D . The linear enhancement load configuration, however, requires a load transistor of larger area
relative to the saturated enhancement load inverter, and requires additional chip area for the VG G contact.
In the depletion NMOS load inverter of Fig. 8.13(c), VG S = 0, thus the load device is always on and VO H
pulls all the way to VD D . This configuration overcomes the area disadvantage without incurring a voltage
swing penalty. It is, therefore, the preferred alternative. The performance of the NMOS inverters with the
four different types of loads are graphically compared in Fig. 8.14(a) and Fig. 8.14(b). Both the loadlines
ID VO
5V
VGS
2.5
(a) 0 1 2 3 4V VDS (b) 0 1 2 3 4V V in
DEPLETION LOAD
RESISTIVE LOAD
LINEAR ENH. LOAD
SATURATED ENH. LOAD
FIGURE 8.14 Performance of NMOS inverters with different types of loads: (a) output characteristics and load lines,
(b) voltage transfer characteristics.
Copyright 2005 by Taylor & Francis Group
, 724 Electronics Handbook
and the voltage transfer characteristics were obtained from SPICE simulation. Figure 8.14(a) shows the
loadlines superimposed on the output characteristics of the pull-down transistor, which is the same for the
four inverters. R L is 100 k and each inverter has VDD = 5 V, VOL = 0.2 V and I D max = 48 µA. Note that
VOH falls short of VDD for the saturated enhancement load inverter but not for the others. Figure 8.14(b)
shows the voltage transfer characteristics (VTC) for the four inverters. VOH is again shown to be less than
VDD for the saturated enhancement load. Note, also, that the depletion load VTC more closely approaches
the ideal inverter VTC than any of the others.
The loadlines of Fig. 8.13(a) are easy to generate. Consider, for example the depletion NMOS load. VG S
is fixed at 0 V, so that its output characteristic consists of only the curve for VG S = 0. I D is always the same
for the load and driving transistor, but their VD S add up to VD D . Thus, when VD S is high for one transistor,
it is low for the other. The loadline is obtained by shifting the origin for VD S for the load characteristic to
VD D , reflecting it about the vertical axis through VD D and superimposing it on the V –I characteristics for
the driving inverter.
The voltage transfer characteristics are best generated by computer simulation. Useful insights, however,
can be gained from an analysis yielding the critical voltages VO H , VO L , VI H , VI L , and VO for any specified
Vin . The NMOS currents hold the key to such an analysis. Threshold voltages are different for enhancement
and depletion NMOS transistors, but the drain current equations are the same. The drain current is given
in the linear region and the saturated region, respectively, by
I D = K n 2(VG S − VT )VD S − VD2 S ; VD S ≤ VG S − VT (8.3)
I D = K n (VG S − VT )2 ; VD S ≥ VG S − VT (8.4)
where
VT = threshold
voltage
Kn = µn2C ox wL = transconductance
µn = electron channel mobility
C ox = gate capacitance per unit area
Similar definitions apply to PMOS transistors.
Consider the VTC of Fig. 8.15(a) for a depletion load NMOS inverter. For the region 0 < Vin < VT the
driving transistor is off, so VO H = VD D . At A, Vin is small; thus, for the driving transistor, VD S = VO >
Vin − VT = VG S − VT . For the load VD S = VD D − VO is small. Hence, the driver is saturated and load
VO VO
5V A 5V
4 4
3 B 3
2 2
1 C 1
0 1 2 3 4 5V V in 0 1 2 3 4 5 V V in
REGIONS GEOMETRIC RATIOS
DRIVER OFF, LOAD LINEAR KR = 2
DRIVER SATURATED, LOAD LINEAR KR = 4
(a) DRIVER LINEAR, LOAD SATURATED (b) KR = 8
FIGURE 8.15 Regions of the VTC and VTCs for different geometric ratios for the depletion load NMOS inverters:
(a) depletion load NMOS inverter VTC and its regions, (b) VTCs for different geometric ratios.
Copyright 2005 by Taylor & Francis Group
