Microelectronics 715
The signal rise time depends on the driver design and the transmission line’s characteristic impedance Z 0 .
In MOS ICs, the load device at the receiving end of the transmission line can always be treated as an open
circuit. Therefore, driver design is a very important aspect of high-speed circuit design. The ideal case
is to have the driver’s output impedance match the transmission line’s characteristic impedance. Driving
an unterminated transmission line (the MOS IC case) with its output impedance lower than the line’s
characteristic impedance, however, can increase driver’s settling time due to excess ringing and, therefore, is
definitely to be avoided. Excess ringing at the receiving end could also cause the load to switch undesirably.
Assuming MOS transistor’s threshold is 0.6–0.8 V, to ensure that no undesirable switching takes place, the
output impedance of the drive should be at least a third of the charactertstic impedance of the transmission
line. When the output impedance is higher than the line’s characteristic impedance, multiple wave trips
of the signal may be required to switch the load. To ensure that only one wave trip is needed to switch
the load, the output impedance of the driver should be within 60% of the characteristic impedance of the
transmission line.
For a lossy transmission line due to parasitic resistance of on-chip interconnects, an exponential
attenuating transfer function can be applied to the signal transfer at any point on the transmission line.
The rate of the attenuation is proportional to the unit resistance of the interconnect. When operating
frequency increases beyond a certain level, the on-chip transmission media exhibits the skin effect in which
the time-varying currents concentrate near the skin of the conductor. Therefore, the unit resistance of the
transmission media increases dramatically.
Defining Terms
Application-specific integrated circuit (ASIC): Device designed specifically for a particular application.
Application-specific standard product (ASSP): Device designed specifically for one area of applications,
such as graphics and video processing.
Asynchronous system: A system in which the progress of a computation is driven by the readiness of all
the necessary input variables for the computation through a handshaking protocol. Therefore, no
central clock is needed.
C-element: A circuit used in an asynchronous as an interconnect circuit. The function of this circuit is to
facilitate the handshaking communication protocol between two functional blocks.
Clock skew: A phase difference between two clock signals at different part of a chip/system due to imbal-
ance of the distribution media and the distribution network.
Complementary metal-oxide silicon (CMOS): It is a very popular integrated circuit type in use today.
Critical path: A signal path from a primary input pin to a primary output pin with the longest delay time
in a logic block.
Delay-locked loop (DLL): It is similar to PLL except that it has better jitter suppression capability.
Digital signal processor (DSP): A processing device specialized in popular math routines used by signal
processing algorithms.
Field programmable gate array (FPGA): A popular device which can be tailored to a particular applica-
tion by loading a customizing program on to the chip.
H-tree: A popular clock distribution tree topologically that resembles the H shape. It introduces the least
amount of clock skew compared to other distribution topologies.
Phase-locked loop (PLL): A circuit that can detect the phase difference of two signals and reduce the
difference in the presence of the phase difference.
Programmable logic devices (PLD): A class of IC products which are easy to customize for a particular
application.
SPICE: A popular circuit level simulation program to perform detailed analysis of circuit behavior.
Synchronous system: A system in which a computation is divided into unit periods defined by a central
clock signal. Signal transfer within the system typically occurred at the transition edge of the clock
signal.
Copyright 2005 by Taylor & Francis Group
, 716 Electronics Handbook
References
Bakoglu, H.B. 1991. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, Reading,
MA.
Dill, D.L. 1989. Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits. MIT
Press, Cambridge, MA.
Gardner, F.M. 1979. Phaselock Techniques, 2nd ed. Wiley, New York.
Jeong, D. et al. 1987. Design of PLL-based clock generation circuits. IEEE J. Solid-State Circuits SC-22(2):
255–261.
Johnson, M. and Hudson, E. 1988. A variable delay line PLL for CPU-coprocessor synchronization. IEEE
J. Solid-State Circuits (Oct.):1218–1223.
Meng, T.H. 1991. Synchronization Design for Digital Systems. Kluwer Academic, Norwell, MA.
Rosenstark, S. 1994. Transmission Lines in Computer Engineering. McGraw-Hill, New York.
Sapatnekar, S., Rao, V., and Vaidya, P. 1992. A convex optimization approach to transistor sizing for CMOS
circuits. Proc. ICCAD, pp. 482–485.
Wang, X. and Chen, T. 1995. Performance and area optimization of VLSI systems using genetic algorithms.
Int. J. of VLSI Design 3(1):43–51.
Weste, N. and Eshraghian, K. 1993. Principle of CMOS VLSI Design: A Systems Perspective, 2nd ed. Addison-
Wesley, Reading, MA.
Further Information
For general information on the VLSI design process and various design issues, consult several excellent
reference books, two of which are listed in the reference section, including Mead and Conway’s Introduction
to VLSI Systems, Glasser and Dobberpuhl’s The Design and Analysis of VLSI Circuits, and Geiger’s VLSI
Design Techniques for Analog and Digital Circuits. IEEE Journal of Solid-State Circuits provides an excellent
source for the latest development of novel and high-performance VLSI devices.
Some of the latest applications of PLLs and DLLs can be found in the Proceedings of International Solid-
State Circuit Conference, the Symposium on VLSI Circuits, and the Custom Integrated Circuit Conference.
For information on modeling of VLSI interconnects and their transmission line treatment, consult
the Proceedings of Design Automation Conference and International Conference on Computer-Aided Design.
IEEE Transactions on CAD is also an excellent source of information on the subject.
8.2 Integrated Circuit Design
Samuel O. Agbo and Eugene D. Fabricius
8.2.1 Introduction
Integrated circuits (ICs) are classified according to their levels of complexity: small-scale integration (SSI),
medium-scale integration (MSI), large-scale integration (LSI) and very large-scale integration (VLSI).
They are also classified according to the technology employed for their fabrication (bipolar, N metal
oxide semiconductor (NMOS), complementary metal oxide semiconductor (CMOS), etc.). The design of
integrated circuits needs to be addressed at the SSI, MSI, LSI, and VLSI levels. Digital SSI and MSI typically
consist of gates and combinations of gates. Design of digital SSI and MSI is presented in Sec. 8.2.3, and
consists largely of the design of standard gates. These standard gates are designed to have large noise
margins, large fan out, and large load current capability, in order to maximize their versatility.
In principle, the basic gates are sufficient for the design of any digital integrated circuit, no matter
how complex. In practice, modifications are necessary in the basic gates and MSI circuits like flip-flops,
registers, adders, etc., when such circuits are to be employed in LSI or VLSI design. For example, circuits
to be interconnected on the same chip can be designed with lower noise margins, reduced load driving
capability, and smaller logic swing. The resulting benefits are lower power consumption, greater circuit
density, and improved reliability. On the other hand, several methodologies have emerged in LSI and VLSI
Copyright 2005 by Taylor & Francis Group
The signal rise time depends on the driver design and the transmission line’s characteristic impedance Z 0 .
In MOS ICs, the load device at the receiving end of the transmission line can always be treated as an open
circuit. Therefore, driver design is a very important aspect of high-speed circuit design. The ideal case
is to have the driver’s output impedance match the transmission line’s characteristic impedance. Driving
an unterminated transmission line (the MOS IC case) with its output impedance lower than the line’s
characteristic impedance, however, can increase driver’s settling time due to excess ringing and, therefore, is
definitely to be avoided. Excess ringing at the receiving end could also cause the load to switch undesirably.
Assuming MOS transistor’s threshold is 0.6–0.8 V, to ensure that no undesirable switching takes place, the
output impedance of the drive should be at least a third of the charactertstic impedance of the transmission
line. When the output impedance is higher than the line’s characteristic impedance, multiple wave trips
of the signal may be required to switch the load. To ensure that only one wave trip is needed to switch
the load, the output impedance of the driver should be within 60% of the characteristic impedance of the
transmission line.
For a lossy transmission line due to parasitic resistance of on-chip interconnects, an exponential
attenuating transfer function can be applied to the signal transfer at any point on the transmission line.
The rate of the attenuation is proportional to the unit resistance of the interconnect. When operating
frequency increases beyond a certain level, the on-chip transmission media exhibits the skin effect in which
the time-varying currents concentrate near the skin of the conductor. Therefore, the unit resistance of the
transmission media increases dramatically.
Defining Terms
Application-specific integrated circuit (ASIC): Device designed specifically for a particular application.
Application-specific standard product (ASSP): Device designed specifically for one area of applications,
such as graphics and video processing.
Asynchronous system: A system in which the progress of a computation is driven by the readiness of all
the necessary input variables for the computation through a handshaking protocol. Therefore, no
central clock is needed.
C-element: A circuit used in an asynchronous as an interconnect circuit. The function of this circuit is to
facilitate the handshaking communication protocol between two functional blocks.
Clock skew: A phase difference between two clock signals at different part of a chip/system due to imbal-
ance of the distribution media and the distribution network.
Complementary metal-oxide silicon (CMOS): It is a very popular integrated circuit type in use today.
Critical path: A signal path from a primary input pin to a primary output pin with the longest delay time
in a logic block.
Delay-locked loop (DLL): It is similar to PLL except that it has better jitter suppression capability.
Digital signal processor (DSP): A processing device specialized in popular math routines used by signal
processing algorithms.
Field programmable gate array (FPGA): A popular device which can be tailored to a particular applica-
tion by loading a customizing program on to the chip.
H-tree: A popular clock distribution tree topologically that resembles the H shape. It introduces the least
amount of clock skew compared to other distribution topologies.
Phase-locked loop (PLL): A circuit that can detect the phase difference of two signals and reduce the
difference in the presence of the phase difference.
Programmable logic devices (PLD): A class of IC products which are easy to customize for a particular
application.
SPICE: A popular circuit level simulation program to perform detailed analysis of circuit behavior.
Synchronous system: A system in which a computation is divided into unit periods defined by a central
clock signal. Signal transfer within the system typically occurred at the transition edge of the clock
signal.
Copyright 2005 by Taylor & Francis Group
, 716 Electronics Handbook
References
Bakoglu, H.B. 1991. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, Reading,
MA.
Dill, D.L. 1989. Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits. MIT
Press, Cambridge, MA.
Gardner, F.M. 1979. Phaselock Techniques, 2nd ed. Wiley, New York.
Jeong, D. et al. 1987. Design of PLL-based clock generation circuits. IEEE J. Solid-State Circuits SC-22(2):
255–261.
Johnson, M. and Hudson, E. 1988. A variable delay line PLL for CPU-coprocessor synchronization. IEEE
J. Solid-State Circuits (Oct.):1218–1223.
Meng, T.H. 1991. Synchronization Design for Digital Systems. Kluwer Academic, Norwell, MA.
Rosenstark, S. 1994. Transmission Lines in Computer Engineering. McGraw-Hill, New York.
Sapatnekar, S., Rao, V., and Vaidya, P. 1992. A convex optimization approach to transistor sizing for CMOS
circuits. Proc. ICCAD, pp. 482–485.
Wang, X. and Chen, T. 1995. Performance and area optimization of VLSI systems using genetic algorithms.
Int. J. of VLSI Design 3(1):43–51.
Weste, N. and Eshraghian, K. 1993. Principle of CMOS VLSI Design: A Systems Perspective, 2nd ed. Addison-
Wesley, Reading, MA.
Further Information
For general information on the VLSI design process and various design issues, consult several excellent
reference books, two of which are listed in the reference section, including Mead and Conway’s Introduction
to VLSI Systems, Glasser and Dobberpuhl’s The Design and Analysis of VLSI Circuits, and Geiger’s VLSI
Design Techniques for Analog and Digital Circuits. IEEE Journal of Solid-State Circuits provides an excellent
source for the latest development of novel and high-performance VLSI devices.
Some of the latest applications of PLLs and DLLs can be found in the Proceedings of International Solid-
State Circuit Conference, the Symposium on VLSI Circuits, and the Custom Integrated Circuit Conference.
For information on modeling of VLSI interconnects and their transmission line treatment, consult
the Proceedings of Design Automation Conference and International Conference on Computer-Aided Design.
IEEE Transactions on CAD is also an excellent source of information on the subject.
8.2 Integrated Circuit Design
Samuel O. Agbo and Eugene D. Fabricius
8.2.1 Introduction
Integrated circuits (ICs) are classified according to their levels of complexity: small-scale integration (SSI),
medium-scale integration (MSI), large-scale integration (LSI) and very large-scale integration (VLSI).
They are also classified according to the technology employed for their fabrication (bipolar, N metal
oxide semiconductor (NMOS), complementary metal oxide semiconductor (CMOS), etc.). The design of
integrated circuits needs to be addressed at the SSI, MSI, LSI, and VLSI levels. Digital SSI and MSI typically
consist of gates and combinations of gates. Design of digital SSI and MSI is presented in Sec. 8.2.3, and
consists largely of the design of standard gates. These standard gates are designed to have large noise
margins, large fan out, and large load current capability, in order to maximize their versatility.
In principle, the basic gates are sufficient for the design of any digital integrated circuit, no matter
how complex. In practice, modifications are necessary in the basic gates and MSI circuits like flip-flops,
registers, adders, etc., when such circuits are to be employed in LSI or VLSI design. For example, circuits
to be interconnected on the same chip can be designed with lower noise margins, reduced load driving
capability, and smaller logic swing. The resulting benefits are lower power consumption, greater circuit
density, and improved reliability. On the other hand, several methodologies have emerged in LSI and VLSI
Copyright 2005 by Taylor & Francis Group
