8
Microelectronics
Tom Chen
Colorado State University
Samuel O. Agbo 8.1 Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
California Polytechnic State University Introduction • High-Speed Design Techniques
Eugene D. Fabricius 8.2 Integrated Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
California Polytechnic State University
Introduction • An Overview of the IC Design Process
• General Considerations in IC Design • Design of Small-Scale
Robert J. Feugate, Jr. and Medium-Scale Integrated Circuits • LSI and VLSI Circuit
University of Arizona Design • Increasing Packing Density and Reducing Power
Dissipation in MOS Circuits • Gate Arrays • Standard Cells
Shih-Lien Lu • Programmable Logic Devices • Reducing Propagation Delays
Oregon State University • Output Buffers
James G. Cottle 8.3 Digital Logic Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Introduction • Transistor-Transistor Logic • CMOS Logic
Hewlett-Packard • Emitter-Coupled Logic • Programmable Logic
Susan A. Garrod 8.4 Memory Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
Purdue University Introduction • Memory Organization • Memory Device Types
• Interfacing Memory Devices • Error Detection and
Constantine N. Correction
Anagnostopoulos 8.5 Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Eastman Kodak Company Introduction • Architecture Basics
Paul P.K. Lee 8.6 D/A and A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
Introduction • D/A and A/D Circuits
Eastman Kodak Company
8.7 Application-Specific Integrated Circuits. . . . . . . . . . . . . . . . 791
Jonathon A. Chambers Introduction • Full Custom ASICs • Semicustom ASICs
Cardiff University 8.8 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
Sawasd Tantaratana Introduction • FIR Filters • Infinite Impulse Response (IIR)
Filters • Finite Wordlength Effects
University of Massachusetts
8.9 Multichip Module Technology . . . . . . . . . . . . . . . . . . . . . . . . 832
Bruce W. Bomar Introduction • Multichip Module Technology Definitions
• Design, Repair, and Test • When to Use Multichip Modules
University of Tennessee Space Institute
• Issues in the Design of Multichip Modules
Paul D. Franzon 8.10 Testing of Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 844
North Carolina State University • • •
Introduction Defect Types Concepts of Test Test
Wayne Needham Tradeoffs
Intel Corporation 8.11 Integrated Circuit Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
Introduction • Surface Mount Packages • Chip-Scale Packaging
Victor Meeldijk • Bare Die • Through-Hole Packages • Module Assemblies
Intel Corporation • Lead Finish • The Future
707
Copyright 2005 by Taylor & Francis Group
, 708 Electronics Handbook
8.1 Integrated Circuits
Tom Chen
8.1.1 Introduction
Transistors and their fabrication into very large scale integrated (VLSI) circuits are the invention that has
made modern computing possible. Since its inception, integrated circuits have been advancing rapidly
from a few transistors on a small silicon die in the early 1960s to 4 millions of transistors integrated on
to a single large silicon substrate. The dominant type of transistor used in today’s integrated circuits is
the metal-oxide-semiconductor (MOS) type transistor. The rapid technological advances in integrated
circuit (IC) technology accelerated during and after the 1980s, and one of the most influential factors for
such a rapid advance is the technology scaling, that is, the reduction in MOS transistor feature sizes. The
MOS feature size is typically measured by the MOS transistor channel length. The smaller the transistors,
the more dense the integrated circuits in terms of the number of transistors packed on to a unit area of
silicon substrate, and the faster the transistor can switch. Not only can we pack more transistors onto a unit
silicon area, the chip size has also increase. As the transistor gets smaller and silicon chip size gets bigger,
the transistor’s driving capability decreases and the interconnect parasitics (interconnect capacitance and
resistance) increases. Consequently, the entire VLSI system has to be designed very carefully to meet the
speed demands of the future. Common design issues include optimal gate design and transistor sizing,
minimization of clock skew and proper timing budgeting, and realistic modeling of interconnect parasitics.
8.1.2 High-Speed Design Techniques
A modern VLSI device typically consists of several megacells, such as memory blocks and data-path
arithmetic blocks, and a lot of basic MOS logic gates, such as inverters and NAND/NOR gates. Comple-
mentary MOS (CMOS) is one of the most widely used logic families, mainly because of its low-power
consumption and high-noise margin. Other logic families include NMOS and PMOS logic. Because of its
popularity, only the CMOS logic will be discussed. Many approaches to high-speed design discussed here
are equally applicable to other logic families.
Optimizing a VLSI device for high-speed operation can be carried out at the system level, as well as at
the circuit and logic level. To achieve the maximum operating speed at the circuit and logic levels for a
given technology, it is essential to properly set the size of each transistor in a logic gate to optimally drive
the output load. If the output load is very large, a string of drivers with geometrically increasing sizes is
needed. The size of transistors in a logic gate is also determined by the impact of the transistors as a load
to be driven by their preceding gates.
VOLTAGE
Optimization of Gate Level Design p-type
transistor V in
To optimize the gate level design, let us look at the Vdd
Vin Vout
performance of a single CMOS inverter as shown Vdd
in Fig. 8.1. Delay of a gate is typically defined as the n-type 2
transistor GATE
time difference between input transition and output DELAY Vout
transition at 50% of supply voltage. The inverter TIME
gate delay can be analytically expressed as
Td = C l (An /βn + A p /β p )/2 FIGURE 8.1 Gate delay in a single inverter.
where C l is the load capacitance of the inverter; βn and β p are the forward current gains of n-type and
p-type transistors, respectively, and are proportional to the transistor’s channel width and inversely pro-
portional to the transistor’s channel length; An and A p are process related parameters for a given supply
voltage and they are determined by
An = [2n/(1 − n) + n((2(1 − n) − V0 )/V0 )][Vdd (1 − n)]
An = [−2 p/(1 + p) + n((2(1 + p) − V0 )/V0 )][Vdd (1 + p)]
Copyright 2005 by Taylor & Francis Group
Microelectronics
Tom Chen
Colorado State University
Samuel O. Agbo 8.1 Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
California Polytechnic State University Introduction • High-Speed Design Techniques
Eugene D. Fabricius 8.2 Integrated Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
California Polytechnic State University
Introduction • An Overview of the IC Design Process
• General Considerations in IC Design • Design of Small-Scale
Robert J. Feugate, Jr. and Medium-Scale Integrated Circuits • LSI and VLSI Circuit
University of Arizona Design • Increasing Packing Density and Reducing Power
Dissipation in MOS Circuits • Gate Arrays • Standard Cells
Shih-Lien Lu • Programmable Logic Devices • Reducing Propagation Delays
Oregon State University • Output Buffers
James G. Cottle 8.3 Digital Logic Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Introduction • Transistor-Transistor Logic • CMOS Logic
Hewlett-Packard • Emitter-Coupled Logic • Programmable Logic
Susan A. Garrod 8.4 Memory Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
Purdue University Introduction • Memory Organization • Memory Device Types
• Interfacing Memory Devices • Error Detection and
Constantine N. Correction
Anagnostopoulos 8.5 Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Eastman Kodak Company Introduction • Architecture Basics
Paul P.K. Lee 8.6 D/A and A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
Introduction • D/A and A/D Circuits
Eastman Kodak Company
8.7 Application-Specific Integrated Circuits. . . . . . . . . . . . . . . . 791
Jonathon A. Chambers Introduction • Full Custom ASICs • Semicustom ASICs
Cardiff University 8.8 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
Sawasd Tantaratana Introduction • FIR Filters • Infinite Impulse Response (IIR)
Filters • Finite Wordlength Effects
University of Massachusetts
8.9 Multichip Module Technology . . . . . . . . . . . . . . . . . . . . . . . . 832
Bruce W. Bomar Introduction • Multichip Module Technology Definitions
• Design, Repair, and Test • When to Use Multichip Modules
University of Tennessee Space Institute
• Issues in the Design of Multichip Modules
Paul D. Franzon 8.10 Testing of Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 844
North Carolina State University • • •
Introduction Defect Types Concepts of Test Test
Wayne Needham Tradeoffs
Intel Corporation 8.11 Integrated Circuit Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
Introduction • Surface Mount Packages • Chip-Scale Packaging
Victor Meeldijk • Bare Die • Through-Hole Packages • Module Assemblies
Intel Corporation • Lead Finish • The Future
707
Copyright 2005 by Taylor & Francis Group
, 708 Electronics Handbook
8.1 Integrated Circuits
Tom Chen
8.1.1 Introduction
Transistors and their fabrication into very large scale integrated (VLSI) circuits are the invention that has
made modern computing possible. Since its inception, integrated circuits have been advancing rapidly
from a few transistors on a small silicon die in the early 1960s to 4 millions of transistors integrated on
to a single large silicon substrate. The dominant type of transistor used in today’s integrated circuits is
the metal-oxide-semiconductor (MOS) type transistor. The rapid technological advances in integrated
circuit (IC) technology accelerated during and after the 1980s, and one of the most influential factors for
such a rapid advance is the technology scaling, that is, the reduction in MOS transistor feature sizes. The
MOS feature size is typically measured by the MOS transistor channel length. The smaller the transistors,
the more dense the integrated circuits in terms of the number of transistors packed on to a unit area of
silicon substrate, and the faster the transistor can switch. Not only can we pack more transistors onto a unit
silicon area, the chip size has also increase. As the transistor gets smaller and silicon chip size gets bigger,
the transistor’s driving capability decreases and the interconnect parasitics (interconnect capacitance and
resistance) increases. Consequently, the entire VLSI system has to be designed very carefully to meet the
speed demands of the future. Common design issues include optimal gate design and transistor sizing,
minimization of clock skew and proper timing budgeting, and realistic modeling of interconnect parasitics.
8.1.2 High-Speed Design Techniques
A modern VLSI device typically consists of several megacells, such as memory blocks and data-path
arithmetic blocks, and a lot of basic MOS logic gates, such as inverters and NAND/NOR gates. Comple-
mentary MOS (CMOS) is one of the most widely used logic families, mainly because of its low-power
consumption and high-noise margin. Other logic families include NMOS and PMOS logic. Because of its
popularity, only the CMOS logic will be discussed. Many approaches to high-speed design discussed here
are equally applicable to other logic families.
Optimizing a VLSI device for high-speed operation can be carried out at the system level, as well as at
the circuit and logic level. To achieve the maximum operating speed at the circuit and logic levels for a
given technology, it is essential to properly set the size of each transistor in a logic gate to optimally drive
the output load. If the output load is very large, a string of drivers with geometrically increasing sizes is
needed. The size of transistors in a logic gate is also determined by the impact of the transistors as a load
to be driven by their preceding gates.
VOLTAGE
Optimization of Gate Level Design p-type
transistor V in
To optimize the gate level design, let us look at the Vdd
Vin Vout
performance of a single CMOS inverter as shown Vdd
in Fig. 8.1. Delay of a gate is typically defined as the n-type 2
transistor GATE
time difference between input transition and output DELAY Vout
transition at 50% of supply voltage. The inverter TIME
gate delay can be analytically expressed as
Td = C l (An /βn + A p /β p )/2 FIGURE 8.1 Gate delay in a single inverter.
where C l is the load capacitance of the inverter; βn and β p are the forward current gains of n-type and
p-type transistors, respectively, and are proportional to the transistor’s channel width and inversely pro-
portional to the transistor’s channel length; An and A p are process related parameters for a given supply
voltage and they are determined by
An = [2n/(1 − n) + n((2(1 − n) − V0 )/V0 )][Vdd (1 − n)]
An = [−2 p/(1 + p) + n((2(1 + p) − V0 )/V0 )][Vdd (1 + p)]
Copyright 2005 by Taylor & Francis Group
