682 Electronics Handbook
METAL METAL
1 2
FIELD OXIDE
POLY 2
THIN OXIDE C
C
POLY 1 1 2
Cp1 FIELD OXIDE Cp 2 Cp1 Cp2
SUBSTRATE
(a) (b)
FIGURE 7.152 Double polysilicon CMOS capacitor and the associated parasitic capacitances: (a) CMOS implemen-
tation, (b) symbolic representation
and it is due to the interconnection of C to other circuitry. Typically, values of C p2 can be from 0.1–1% of
C , depending on the layout technique.
Recognizing that the range of capacitance values of the capacitors used as passive components in SC
filters are typically from 0.01 to 100 pF, therefore, the effects of this parasitic on the frequency response
should not be ignored. The design of SC filters must be done in such a way that the parasitic capacitors do
not degrade the performance of the filter, as will be seen later.
The effect of the parasitic capacitors is shown in Fig. 7.153 for the FEDI. Most of the top and bottom
plate parasitic capacitors, shown in Fig. 7.153(a), have no effect on V2 since they do not deliver any charge
to C 2 (C p12 , C pn22 , and C p21 are shorted assuming that the open-loop gain of the op amp is sufficiently
high, C pn11 and C p22 are voltage driven and, therefore, they are insignificant). The overlap capacitance
C2
f f
C p12 C p22
Col1 Col1 Col2 Col2
−
V1
+ V2
C pn11 C1 C pn21 C pn22
C pn12 C p11
C p 21
(a)
f f
C2
−
V1
+ V2
Cp C1
(b)
FIGURE 7.153 Management of parasitic capacitances: (a) SC integrator and the associated parasitic capacitances,
(b) effect of the parasitics on the performance of SC integrator.
Copyright 2005 by Taylor & Francis Group
, Semiconductor Devices and Circuits 683
(C ol1 and C ol2 ) can be drastically reduced in the fabrication process (using the self-alignment techniques),
therefore, they are irrelevant. The parasitic capacitors that have direct effect on the output of the integrator
are C pn12 , C p11 , and C pn21 . Their parallel combination is represented by C p as shown in Fig. 7.153(b). C p
is poorly controlled and may be as large as 0.05 pF, making the net value of C 1 uncertain. If, for example,
1% accuracy is required for C 1 , it should have value greater than 5 pF. For practical reasons, the integrating
capacitance C 2 C 1 ; therefore, the integrator will consume a large chip area.
7.9.5 Parasitic-Insensitive Switched-Capacitor Integrators
The effect of the parasitic capacitors can be eliminated by the use of the parasitic-insensitive integrator
configurations (Hosticka, Brodersen, and Gray, 1977; Mertin and Sedra, 1979), shown in Fig. 7.154. The
circuit in Fig. 7.154(a) is the parasitic-insensitive version of the FEDI, where C 1 is charging through the top
plate and discharging through the bottom plate. Therefore, the transfer function of this integrator, with
ν2 is sampled when φ is high, is a noninverting one. It should be noted that if ν1 is sampled and held for a
full-clock cycle, then ν2 will also be held constant for a full cycle. The integrator shown in Fig. 7.154(c) has
an inverting transfer function. Applying the charge equation method, previously described in Sec. 7.9.3,
to the integrator of Fig. 7.154(c) and assuming ν2 is sampled when φ is high, one can easily derive the
following transfer function:
V2 C1 1
(z) = − (7.223)
V1 C2 1 − z −1
It should be noted that the numerical integration in Eq. (7.223) is similar to the backward-Euler numerical
integration scheme. Therefore, the integrator in Fig. 7.154(c), with the output signal sampled when φ is
high, is known as the backward-Euler discrete integrator (BEDI).
The MOS implementations along with the relevant parasitic capacitors, C p1 and C p2 , are also given
in Fig. 7.154(b) and Fig. 7.154(d). Note that C p1 and C p2 are periodically switched between ν1 ground
and the op amp’s virtual ground-ground, respectively. Therefore, they do not deliver any charge to C 2 .
C2
f f C2
C1
C1 −
V1 −
+ V2 V1
+ V2
C p1 C p2
f f
(a) (b)
C2
f f C2
C1
C1 −
V1 −
+ V2 V1
+ V2
C p1 C p2
f f
(c) (d)
FIGURE 7.154 (a) Parasitic-insensitive FEDI, (b) MOS realization of (a), (c) parasitic-insensitive BEDI, (d) MOS
realization of (c).
Copyright 2005 by Taylor & Francis Group
METAL METAL
1 2
FIELD OXIDE
POLY 2
THIN OXIDE C
C
POLY 1 1 2
Cp1 FIELD OXIDE Cp 2 Cp1 Cp2
SUBSTRATE
(a) (b)
FIGURE 7.152 Double polysilicon CMOS capacitor and the associated parasitic capacitances: (a) CMOS implemen-
tation, (b) symbolic representation
and it is due to the interconnection of C to other circuitry. Typically, values of C p2 can be from 0.1–1% of
C , depending on the layout technique.
Recognizing that the range of capacitance values of the capacitors used as passive components in SC
filters are typically from 0.01 to 100 pF, therefore, the effects of this parasitic on the frequency response
should not be ignored. The design of SC filters must be done in such a way that the parasitic capacitors do
not degrade the performance of the filter, as will be seen later.
The effect of the parasitic capacitors is shown in Fig. 7.153 for the FEDI. Most of the top and bottom
plate parasitic capacitors, shown in Fig. 7.153(a), have no effect on V2 since they do not deliver any charge
to C 2 (C p12 , C pn22 , and C p21 are shorted assuming that the open-loop gain of the op amp is sufficiently
high, C pn11 and C p22 are voltage driven and, therefore, they are insignificant). The overlap capacitance
C2
f f
C p12 C p22
Col1 Col1 Col2 Col2
−
V1
+ V2
C pn11 C1 C pn21 C pn22
C pn12 C p11
C p 21
(a)
f f
C2
−
V1
+ V2
Cp C1
(b)
FIGURE 7.153 Management of parasitic capacitances: (a) SC integrator and the associated parasitic capacitances,
(b) effect of the parasitics on the performance of SC integrator.
Copyright 2005 by Taylor & Francis Group
, Semiconductor Devices and Circuits 683
(C ol1 and C ol2 ) can be drastically reduced in the fabrication process (using the self-alignment techniques),
therefore, they are irrelevant. The parasitic capacitors that have direct effect on the output of the integrator
are C pn12 , C p11 , and C pn21 . Their parallel combination is represented by C p as shown in Fig. 7.153(b). C p
is poorly controlled and may be as large as 0.05 pF, making the net value of C 1 uncertain. If, for example,
1% accuracy is required for C 1 , it should have value greater than 5 pF. For practical reasons, the integrating
capacitance C 2 C 1 ; therefore, the integrator will consume a large chip area.
7.9.5 Parasitic-Insensitive Switched-Capacitor Integrators
The effect of the parasitic capacitors can be eliminated by the use of the parasitic-insensitive integrator
configurations (Hosticka, Brodersen, and Gray, 1977; Mertin and Sedra, 1979), shown in Fig. 7.154. The
circuit in Fig. 7.154(a) is the parasitic-insensitive version of the FEDI, where C 1 is charging through the top
plate and discharging through the bottom plate. Therefore, the transfer function of this integrator, with
ν2 is sampled when φ is high, is a noninverting one. It should be noted that if ν1 is sampled and held for a
full-clock cycle, then ν2 will also be held constant for a full cycle. The integrator shown in Fig. 7.154(c) has
an inverting transfer function. Applying the charge equation method, previously described in Sec. 7.9.3,
to the integrator of Fig. 7.154(c) and assuming ν2 is sampled when φ is high, one can easily derive the
following transfer function:
V2 C1 1
(z) = − (7.223)
V1 C2 1 − z −1
It should be noted that the numerical integration in Eq. (7.223) is similar to the backward-Euler numerical
integration scheme. Therefore, the integrator in Fig. 7.154(c), with the output signal sampled when φ is
high, is known as the backward-Euler discrete integrator (BEDI).
The MOS implementations along with the relevant parasitic capacitors, C p1 and C p2 , are also given
in Fig. 7.154(b) and Fig. 7.154(d). Note that C p1 and C p2 are periodically switched between ν1 ground
and the op amp’s virtual ground-ground, respectively. Therefore, they do not deliver any charge to C 2 .
C2
f f C2
C1
C1 −
V1 −
+ V2 V1
+ V2
C p1 C p2
f f
(a) (b)
C2
f f C2
C1
C1 −
V1 −
+ V2 V1
+ V2
C p1 C p2
f f
(c) (d)
FIGURE 7.154 (a) Parasitic-insensitive FEDI, (b) MOS realization of (a), (c) parasitic-insensitive BEDI, (d) MOS
realization of (c).
Copyright 2005 by Taylor & Francis Group
