ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY
1.4 MEMORY STRUCTURE IN 8085 PROCESSOR
Memory Structure and Its Requirements:
• Read/Write memory is a group of registers to store binary information. Fig 1.4.1
shows a typical R/W memory chip; it has “2n = M” registers (where n= no. of
address lines) and each can store N no. of bits.
• It has N no. of bidirectional (or separate input-output) data lines.
• It also has one Chip select (CS), and two control lines Read (RD) to enable the
output buffer and Write (WR) to enable the input buffer.
• Figure. 1.4.1 shows the logic diagram of typical EPROM (Erasable
Programmable
Read Only memory) Memory with “2n = M” registers (where n= no. of address
lines).
• It has “n” no. of address lines, one Chip select (CS) and one Read (RD).
• This memory chip must be programmed before it can be used as Read-Only
memory.
Figure 1.4.1 logic diagram of typical EPROM
[Source: “Microprocessor Architecture Programming and Application” by R.S. Gaonkar, page-91]
EE8551 MICROPROCESSOR AND MICROCONTROLLER
, ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY
The 8085 microprocessor uses a16-bit wide address bus for addressing memories
and I/O devices. Using 16-bit wide address bus it can access 216 = 64K bytes of
memory and I/O devices. The 64K addresses are to be assigned to memories and I/O
devices for their addressing. There are two schemes for the allocation of addresses to
memories and input / output devices:
1. Memory mapped I/O scheme.
2. I/O mapped I/O scheme.
Memory mapped I/O scheme:
• In memory mapped I/O scheme there is only one address space.
• Address space is defined as the set of all possible addresses that microprocessor
can generate.
• Some addresses are assigned to memories and some addresses to I/O devices.
• An I/O device is also treated as memory location and one address is assign to it.
• Suppose that memory locations are assigned the addresses 2000 H to 24FF H
then each one address is assign to each memory location. The addresses for I/O
devices are different from the addresses which have been assigned to memories.
• The addresses which have not been assigned to memories can be assigned to each
I/O device.
• In this scheme all the data transfer instructions of the microprocessor can be valid
for data transfer from the memory location or I/O device whose address is in H-L
pair.
I/O mapped I/O scheme:
• In this scheme the addresses assigned to memory location can also be assigned to
I/O devices.
• Since the same address may be assigned to memory location or an I/O device, the
microprocessor must issue a signal to distinguish whether the address on the
address bus is for a memory location or an I/O device.
• The 8085 issues an IO/M signal for this purpose.
EE8551 MICROPROCESSOR AND MICROCONTROLLER
1.4 MEMORY STRUCTURE IN 8085 PROCESSOR
Memory Structure and Its Requirements:
• Read/Write memory is a group of registers to store binary information. Fig 1.4.1
shows a typical R/W memory chip; it has “2n = M” registers (where n= no. of
address lines) and each can store N no. of bits.
• It has N no. of bidirectional (or separate input-output) data lines.
• It also has one Chip select (CS), and two control lines Read (RD) to enable the
output buffer and Write (WR) to enable the input buffer.
• Figure. 1.4.1 shows the logic diagram of typical EPROM (Erasable
Programmable
Read Only memory) Memory with “2n = M” registers (where n= no. of address
lines).
• It has “n” no. of address lines, one Chip select (CS) and one Read (RD).
• This memory chip must be programmed before it can be used as Read-Only
memory.
Figure 1.4.1 logic diagram of typical EPROM
[Source: “Microprocessor Architecture Programming and Application” by R.S. Gaonkar, page-91]
EE8551 MICROPROCESSOR AND MICROCONTROLLER
, ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY
The 8085 microprocessor uses a16-bit wide address bus for addressing memories
and I/O devices. Using 16-bit wide address bus it can access 216 = 64K bytes of
memory and I/O devices. The 64K addresses are to be assigned to memories and I/O
devices for their addressing. There are two schemes for the allocation of addresses to
memories and input / output devices:
1. Memory mapped I/O scheme.
2. I/O mapped I/O scheme.
Memory mapped I/O scheme:
• In memory mapped I/O scheme there is only one address space.
• Address space is defined as the set of all possible addresses that microprocessor
can generate.
• Some addresses are assigned to memories and some addresses to I/O devices.
• An I/O device is also treated as memory location and one address is assign to it.
• Suppose that memory locations are assigned the addresses 2000 H to 24FF H
then each one address is assign to each memory location. The addresses for I/O
devices are different from the addresses which have been assigned to memories.
• The addresses which have not been assigned to memories can be assigned to each
I/O device.
• In this scheme all the data transfer instructions of the microprocessor can be valid
for data transfer from the memory location or I/O device whose address is in H-L
pair.
I/O mapped I/O scheme:
• In this scheme the addresses assigned to memory location can also be assigned to
I/O devices.
• Since the same address may be assigned to memory location or an I/O device, the
microprocessor must issue a signal to distinguish whether the address on the
address bus is for a memory location or an I/O device.
• The 8085 issues an IO/M signal for this purpose.
EE8551 MICROPROCESSOR AND MICROCONTROLLER
