Introduction to Hardware Description Language
I. LESSON TITLE
1. Advantages of HDL
2. Overview of Verilog HDL
3. Introduction to VHDL
4. Features of VHDL
Structure of VHDL
Program
II. LESSON OVERVIEW
The lesson will discuss the fundamentals of Hardware Description Language (HDL)
III. DESIRED LEARNING OUTCOMES
At the end of the lesson, the students should be able to:
Demonstrate understanding in the difference between Verilog and VHDL
Calculate the functionality of Verilog and VHDL
IV. LESSON CONTENT
HARDWARE DESCRIPTION LANGUAGE
A hardware description language (HDL) is a computer-based language that
describes the hardware of digital systems in a textual form.
In electronics a HDL is a language from a class of computer language
for formal description of electronic circuit.
It can describe circuit operation, its design and tests to verify its operation at
any level.
The automatic translation of design description into a set of logic equation is
performed by HDL.
HDL are used to describe the architecture and behavior of discrete electronic
system.
HDL are programming language that have been designed and optimized for
digital circuit design and modeling.
HDLs are used in several major steps in the design flow of an integrated circuit:
1. Design entry creates an HDL-based description of the functionality that is
to be implemented in hardware. Depending on the HDL, the description
can be in a variety of forms: Boolean logic equations, truth tables, a
netlist of interconnected gates, or an abstract behavioral model.
, 2. Logic simulation displays the behavior of a digital system through the use
of a computer.
3. Logic synthesis is the process of deriving a list of physical components
and their interconnections (called a netlist) from the model of a digital
system described in an HDL.
4. Timing verification confirms that the fabricated, integrated circuit will
operate at a specified speed.
5. In VLSI circuit design, fault simulation compares the behavior of an ideal
circuit with the behavior of a circuit that contains a process-induced flaw.
ADVANTAGES OF HARDWARE DESCRIPTION LANGUAGE (HDL)
HDL’s has several advantages over traditional design methodology, they are:
1. We can verify design functionality early in the design written as an HDL
description.
2. Design simulation at this higher level before implementation at gate level,
allow you to test architecture and design decision.
3. Reduced non-recurring engineering costs.
4. Design reused is enabled.
5. Increase flexibility to design changes.
6. Better and easier design auditing and verification.
Two standard HDLs that are supported by the IEEE (Institute of Electrical and
Electronics Engineers): VHDL and VERILOG
VHDL is a Department of Defense–mandated language. (The V in VHDL
stands for the first letter in VHSIC, an acronym for very high-speed
integrated circuit.)
Verilog began as a proprietary HDL of Cadence Design Systems, but
Cadence transferred control of Verilog to a consortium of companies and
universities known as Open Verilog International (OVI) as a step leading to
its adoption as an IEEE standard.
*VHDL is more difficult to learn than Verilog.
MODULE DECLARATION
1. Keywords
- predefined lowercase identifiers that define the language constructs (e.g.,
module, endmodule, input, output, wire, and, or, and not).
2. Comments
- two forward slashes ( // ) and the end of the line
interpreted as a comment and will have no effect on a simulation using the
I. LESSON TITLE
1. Advantages of HDL
2. Overview of Verilog HDL
3. Introduction to VHDL
4. Features of VHDL
Structure of VHDL
Program
II. LESSON OVERVIEW
The lesson will discuss the fundamentals of Hardware Description Language (HDL)
III. DESIRED LEARNING OUTCOMES
At the end of the lesson, the students should be able to:
Demonstrate understanding in the difference between Verilog and VHDL
Calculate the functionality of Verilog and VHDL
IV. LESSON CONTENT
HARDWARE DESCRIPTION LANGUAGE
A hardware description language (HDL) is a computer-based language that
describes the hardware of digital systems in a textual form.
In electronics a HDL is a language from a class of computer language
for formal description of electronic circuit.
It can describe circuit operation, its design and tests to verify its operation at
any level.
The automatic translation of design description into a set of logic equation is
performed by HDL.
HDL are used to describe the architecture and behavior of discrete electronic
system.
HDL are programming language that have been designed and optimized for
digital circuit design and modeling.
HDLs are used in several major steps in the design flow of an integrated circuit:
1. Design entry creates an HDL-based description of the functionality that is
to be implemented in hardware. Depending on the HDL, the description
can be in a variety of forms: Boolean logic equations, truth tables, a
netlist of interconnected gates, or an abstract behavioral model.
, 2. Logic simulation displays the behavior of a digital system through the use
of a computer.
3. Logic synthesis is the process of deriving a list of physical components
and their interconnections (called a netlist) from the model of a digital
system described in an HDL.
4. Timing verification confirms that the fabricated, integrated circuit will
operate at a specified speed.
5. In VLSI circuit design, fault simulation compares the behavior of an ideal
circuit with the behavior of a circuit that contains a process-induced flaw.
ADVANTAGES OF HARDWARE DESCRIPTION LANGUAGE (HDL)
HDL’s has several advantages over traditional design methodology, they are:
1. We can verify design functionality early in the design written as an HDL
description.
2. Design simulation at this higher level before implementation at gate level,
allow you to test architecture and design decision.
3. Reduced non-recurring engineering costs.
4. Design reused is enabled.
5. Increase flexibility to design changes.
6. Better and easier design auditing and verification.
Two standard HDLs that are supported by the IEEE (Institute of Electrical and
Electronics Engineers): VHDL and VERILOG
VHDL is a Department of Defense–mandated language. (The V in VHDL
stands for the first letter in VHSIC, an acronym for very high-speed
integrated circuit.)
Verilog began as a proprietary HDL of Cadence Design Systems, but
Cadence transferred control of Verilog to a consortium of companies and
universities known as Open Verilog International (OVI) as a step leading to
its adoption as an IEEE standard.
*VHDL is more difficult to learn than Verilog.
MODULE DECLARATION
1. Keywords
- predefined lowercase identifiers that define the language constructs (e.g.,
module, endmodule, input, output, wire, and, or, and not).
2. Comments
- two forward slashes ( // ) and the end of the line
interpreted as a comment and will have no effect on a simulation using the
