Summary COMBINATIONAL LOGIC

COMBINATIONAL LOGIC
I. LESSON TITLE:

1. Gate-Level (Structural) Modeling
2. Behavioral Modeling
3. Dataflow Modeling
4. Writing a Simple Test Bench

II. LESSON OVERVIEW

Logic circuits for digital systems may be combinational or sequential. A logic circuit is
combinational if its output at any time are function of only the present inputs. In this
lesson you’ll learn the combinational logic circuits which are the gate-level, dataflow and
behavioural modelling and you’ll be able to write a simple testbench.

III. DESIRED LEARNING OUTCOMES:

At the end of the lesson, the students should be able to:
1. understand the distinction between gate-level, dataflow, and behavioural modelling with
HDL’s
2. able to write a gate-level Verilog
3. write a Verilog continuous assignment statement
4. write a HDL model of combinational logic circuit
5. write a simple testbench

IV. LESSON CONTENT:

HDL MODELS OF COMBINATIONAL CIRCUITS


A. GATE-LEVEL (STRUCTURAL) MODELING
 Gate-level modelling, also called structural modelling.
 Specifies a logic circuit by its gates and their interconnections.
 Provides a textual description of a logic (schematic) diagram.

Unknown and High Impedance

, Verilog Statement of Vectors

In many designs it is helpful to use identifiers having multiple bit widths, called
vectors. The syntax specifying a vector includes within square brackets two whole
numbers separated with colon. The following Verilog statements specify two vectors:

output [0: 3] D;
wire [7: 0] SUM;

HDL Example 1.1 (Gate-level: Two-to-Four-Line Decoder)

The gate-level description of two-to-four-line decoder has two data inputs A
and B and an enable input E. The four outputs are specified with the vector D.




Figure 1. Gate-level: Logic Diagram of Two-to-Four-Line Decoder




Practice Exercise (Two-to-Four-Line Decoder)