CSE/EEE 120
Simulation Lab 4 Answer Sheet
The Microprocessor
Name: Noel Beyard
Date: 11/27/2016
Task 4-1: Build the Brainless Central Processing Unit
Include a picture of your Logisim Brainless Central Processing Unit circuit here:
Task 4-2: Test and Control the Brainless Central Processing Unit
Perform the testing procedures outlined in the laboratory manual and fill in the blanks below. (Note
that these questions appear in the text of the laboratory manual.)
Record the first number placed on the data bus here: 5
What do the following three switches need to be set to in order to perform the pass-through
operation? /~A_Only = 0 /~Invert= 1 Logic/~Arith= X (don’t care)
Enter the second number you entered into the data bus here: 1
What do the following three switches need to be set to in order to perform the ADD operation?
/~A_Only = 1 /~Invert= 1 Logic/~Arith= 0
Write down the number that appears in the accumulator here: 6
1
,Describe other numerical additions and other operations you checked in order to verify your brainless
CPU here: I toggled the clock input (twice) multiple times to see that it would add “1” to each
previous total. I also placed different numbers on the data bus toggled the clock input pin twice to
lock the output of the ALU into the Accumulator, then added a new number into the data bus, toggled
the clock twice and validated that it was adding the number to the stored sum.
After you are convinced your circuit is working properly, remove the 4-bit binary keyboard and set the
ACC to Data Bus pin to 1. Did the output of the accumulator appear on the data bus? Yes
How does the output of the ALU change? It changes from an error to the sum (output of the
Accumulator + output of the Accumulator).
If the 4-bit binary keyboard was not removed and the ACC to Data Bus switch is set to 1, what would you
expect to see displayed in the hex digit display attached to the data bus? I would expect to see a data
conflict (an error), we would have the output of the Accumulator being fed into the output of the 4-bit
binary keyboard, the only way this would not cause an error is if the binary keyboard output is the
same as the Accumulator output.
Add the 4-bit binary keyboard back into your circuit and observe the hex digit display on the data bus for
various keyboard values. Is the value on the hex digit display what you expected? Yes
Explain: The Data Bus cannot receive two different inputs; it will cause a data error. Enabling the 3
state buffer (setting ACC to Data Bus = 1), allows the pass through of the output of the Accumulator
Register to the Data Bus.
Why do you think the register at the output of the ALU is called the ‘accumulator’? It accumulates or
stores the output of the ALU at rise of every clock toggle.
Task 4-3: Build the Addressing Logic
Include a picture of your Logisim addressing logic circuit here:
2
, Test your circuit and record the results in Table 1. Include a picture of your Logisim addressing logic
circuit testing set up.
Table 1
A
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
(4-bit binary)
0000 1 0 0 0 0 0 0 0
0001 0 1 0 0 0 0 0 0
0101 0 0 0 0 0 1 0 0
0111 0 0 0 0 0 0 0 1
3
Simulation Lab 4 Answer Sheet
The Microprocessor
Name: Noel Beyard
Date: 11/27/2016
Task 4-1: Build the Brainless Central Processing Unit
Include a picture of your Logisim Brainless Central Processing Unit circuit here:
Task 4-2: Test and Control the Brainless Central Processing Unit
Perform the testing procedures outlined in the laboratory manual and fill in the blanks below. (Note
that these questions appear in the text of the laboratory manual.)
Record the first number placed on the data bus here: 5
What do the following three switches need to be set to in order to perform the pass-through
operation? /~A_Only = 0 /~Invert= 1 Logic/~Arith= X (don’t care)
Enter the second number you entered into the data bus here: 1
What do the following three switches need to be set to in order to perform the ADD operation?
/~A_Only = 1 /~Invert= 1 Logic/~Arith= 0
Write down the number that appears in the accumulator here: 6
1
,Describe other numerical additions and other operations you checked in order to verify your brainless
CPU here: I toggled the clock input (twice) multiple times to see that it would add “1” to each
previous total. I also placed different numbers on the data bus toggled the clock input pin twice to
lock the output of the ALU into the Accumulator, then added a new number into the data bus, toggled
the clock twice and validated that it was adding the number to the stored sum.
After you are convinced your circuit is working properly, remove the 4-bit binary keyboard and set the
ACC to Data Bus pin to 1. Did the output of the accumulator appear on the data bus? Yes
How does the output of the ALU change? It changes from an error to the sum (output of the
Accumulator + output of the Accumulator).
If the 4-bit binary keyboard was not removed and the ACC to Data Bus switch is set to 1, what would you
expect to see displayed in the hex digit display attached to the data bus? I would expect to see a data
conflict (an error), we would have the output of the Accumulator being fed into the output of the 4-bit
binary keyboard, the only way this would not cause an error is if the binary keyboard output is the
same as the Accumulator output.
Add the 4-bit binary keyboard back into your circuit and observe the hex digit display on the data bus for
various keyboard values. Is the value on the hex digit display what you expected? Yes
Explain: The Data Bus cannot receive two different inputs; it will cause a data error. Enabling the 3
state buffer (setting ACC to Data Bus = 1), allows the pass through of the output of the Accumulator
Register to the Data Bus.
Why do you think the register at the output of the ALU is called the ‘accumulator’? It accumulates or
stores the output of the ALU at rise of every clock toggle.
Task 4-3: Build the Addressing Logic
Include a picture of your Logisim addressing logic circuit here:
2
, Test your circuit and record the results in Table 1. Include a picture of your Logisim addressing logic
circuit testing set up.
Table 1
A
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
(4-bit binary)
0000 1 0 0 0 0 0 0 0
0001 0 1 0 0 0 0 0 0
0101 0 0 0 0 0 1 0 0
0111 0 0 0 0 0 0 0 1
3
