Mixed Signal Design UNIT 1

16EC6DCMSD Mixed Signal Design
6th Semester B. E. Class Notes


Dr. Rajath Vasudevamurthy

,Contents

1 Physics of MOS Transistors 3
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.1 Why Silicon? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.2 CMOS Fabrication Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.3 Photolithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Physics of MOS Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 Transistor Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2 Modeling of the MOS Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.3 Transconductance and Output Characteristics . . . . . . . . . . . . . . . . . . . 6
1.2.4 Channel length modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.5 Body effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.6 Velocity Saturation Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Small-signal model (low frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.2 Small-signal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Transistor biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Single Stage Amplifiers 14
2.1 Common Source amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.1 Resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.2 PMOS (current source) load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.3 Diode-connected load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Common Source amplifier with source degeneration . . . . . . . . . . . . . . . . . . . . 17
2.3 Source follower (Common Drain Amplifier) . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 Common Gate amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5 CS-CG cascode amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5.1 Superior gain than single transistor for same voltage swing . . . . . . . . . . . . 23
2.5.2 Shielding property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.6 Folded Cascode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.7 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3 Current Mirrors 26
3.1 Basic Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.1 Current Mirror with Source Degeneration . . . . . . . . . . . . . . . . . . . . . 27
3.2 Cascode Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.1 Cascode Current Mirror with Improved Output Voltage Swing . . . . . . . . . . 29
3.2.2 Low voltage current mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29




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, Chapter 1

Physics of MOS Transistors

1.1 Introduction
1.1.1 Why Silicon?
• The same silicon substance can be converted to an insulator by oxidation (SiO2 ) and its conduc-
tivity can be precisely controlled by controlling the doping.
• Since both insulator and conductor are developed on the same material, the crystal defects which
can occur while interfacing different materials can be avoided.
• Materials of n-type and p-type conductivity can be prepared by doping with pentavalent (Ex: phos-
phorous, arsenic) and trivalent (Ex: boron, aluminum) impurities respectively.

1.1.2 CMOS Fabrication Process
Sequence of steps necessary to fabricate n-channel (NMOS) and p-channel (PMOS) transistors starting
from a 99.99% pure silicon wafer is described below. The entire silicon wafer is lightly doped with
trivalent impurity to make p− bulk substrate. NMOS transistors are fabricated on this p− substrate, while
PMOS transistors need to be fabricated in an n-well.
Oxidation The topmost layer of silicon wafer is oxidized by passing oxygen to create an insulation layer
(SiO2 ) and for protection
Etch oxide The oxide is etched away from those regions where transistors need to be fabricated by the
process of photolithography
Diffusion for n-well Pentavalent impurities are diffused into the regions where PMOS transistors are
desired to create an n-well
Deposition field oxide for isolation between transistors. In the newer technologies, a shallow trench is
formed in the substrate and filled with an insulating material for isolation. Trench isolation allows
closes placement of transistors as compared to field oxide isolation.
Poly-deposition to create the gate of the transistors.
Diffusion for source & drains Pentavalent impurities for NMOS and trivalent impurities for PMOS
transistors
Deposition of oxide for insulation and protection of lower layers
Drilling through the oxide to create contacts for source, drain, gate (and bulk) terminals
Deposition of Metal 1 to create desired connections between transistors and power supply
After each step, the topmost layer of the wafer has to be maintained perfectly horizontal so that no
gradient in deposition or diffusion occurs in the subsequent steps. Also, perfect alignment of the wafer
as it goes through the various processes listed above has to be ensured so that the orientation of the
transistors are as desired.

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