ANALOG AND DIGITAL ELECTRONICS
18CS33
MODULE – 5
REGISTERS AND COUNTERS
A register consists of a group of flip-flops with a common clock input. Registers are commonly used to
store and shift binary data.
Counters are another simple type of sequential circuits. A counter is usually constructed from two or
more flip-flops which change states in a prescribed sequence when input pulses are received.
REGISTERS AND REGISTER TRANSFERS:
Several D flip-flops may be grouped together with a common clock to form a register (SEE THE
FOLLOWING Figure). Since each flip-flop can store one bit of information, this register can store four
bits of information. This register has a load signal that is ANDed with the clock.
When Load = 0, the register is not clocked, and it holds its present value. Load = 1, the clock signal (Clk)
is transmitted to the flip-flop clock inputs and the data applied to the D inputs will be loaded into the flip-
flops on the falling edge of the clock.
For example, if the Q outputs are 0000 (Q3 = Q2 = Q1 = Q0 = 0) and the data inputs are 1101 (D3 = 1,
D2 = 1, D1 = 0 and D0 = 1), after the falling edge of clock, Q will change from 0000 to 1101 as indicated
in the above Figure (The notation 0 → 1 at the flip-flop outputs indicates a change from 0 to 1).
The flip-flops in the register have asynchronous clear inputs that are connected to a common clear signal,
ClrN. The bubble at the clear inputs indicates that a logic 0 is required to clear the flip-flops. ClrN is
normally 1, and if it is changed momentarily to 0, the Q outputs of all four flip-flops will become 0.
Gating the clock with another signal can cause timing problems. If flip-flops with clock enable are
available, the register can be designed as shown in the following Figure (b).
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, ANALOG AND DIGITAL ELECTRONICS
18CS33
The load signal is connected to all four CE inputs. When Load = 0, the clock is disabled and the register
holds its data. When Load = 1, the clock is enabled, and the data applied to the D inputs will be loaded
into the flip-flops, following the falling edge of the clock.
Figure (c) shows a symbol for the 4-bit register using bus notation for the D inputs and Q outputs. A
group of wires that perform a common function is often referred to as a bus. A heavy line is used to
represent a bus, and a slash with a number beside it indicates the number of bits in the bus.
Transferring data between registers is a common operation in digital systems. The following Figure
shows how data can be transferred from the output of one of two registers into a third register using tri-
state buffers.
If En = 1 and Load = 1, the output of register A is enabled onto the tri-state bus and the data in register A
will be stored in Q after the rising edge of the clock. If En = 0 and Load = 1, the output of register B will
be enabled onto the tri-state bus and stored in Q after the rising edge of the clock.
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, ANALOG AND DIGITAL ELECTRONICS
18CS33
The following Figure (a) shows an integrated circuit register that contains eight D flip-flops with tri-state
buffers at the flip-flop outputs. These buffers are enabled when En = 0. A symbol for this 8-bit register is
shown in Figure (b).
The following Figure (c) shows how data can be transferred from one of four 8-bit registers into one of
two other registers. Registers A, B, C, and D are of the type shown in above Figure.
The outputs from these registers are all connected in parallel to a common tri-state bus. Registers G and H
are 8-bit D type registers (PIPO). The flip-flop inputs of registers G and H are also connected to the bus.
When EnA = 0, the tri-state outputs of register A are enabled onto the bus. If LdG = 1, these signals on
the bus are loaded into register G after the rising clock edge (or into register H if LdH = 1). Similarly, the
data in register B, C, or D is transferred to G (or H) when EnB, EnC, or EnD is 0, respectively and LdG =
1 (or LdH = 1). If LdG = LdH = 1, both G and H will be loaded from the bus. The four enable signals
may be generated by a decoder. The operation can be summarized as follows:
If EF = 00, A is stored in G (or H) If EF = 01, B is stored in G (or H).
If EF = 10, C is stored in G (or H) If EF = 11, D is stored in G (or H).
Note that 8 bits of data are transferred in parallel from register A, B, C, or D to register G or H. As an
alternative to using a bus with tri-state logic, eight 4-to-1 multiplexers could be used, but this would lead
to a more complex circuit.
3
, ANALOG AND DIGITAL ELECTRONICS
18CS33
Parallel Adder with Accumulator:
In computer circuits, it is frequently desirable to store one number in a register of flip-flops (called an
accumulator) and add a second number to it, leaving the result stored in the accumulator.
One way to build a parallel adder with an accumulator is to add a register to the adder as shown in the
following Figure.
Suppose that the number X = xn . . . x2x1 is stored in the accumulator. Then, the number Y = yn . . . y2y1 is
applied to the full adder inputs, and after the carry has propagated through the adders, the sum of X and Y
appears at the adder outputs. An add signal (Ad) is used to load the adder outputs into the accumulator
flip-flops on the rising clock edge. If si = 1, the next state of flip-flop xi will be 1. If si = 0, the next state
of flip-flop xi will be 0.Thus, xi+ = si, and if Ad = 1, the number X in the accumulator is replaced with the
sum of X and Y, following the rising edge of the clock.
Observe that the adder with accumulator is an iterative structure that consists of a number of identical
cells. Each cell contains a full adder and an associated accumulator flip-flop. Cell i, which has inputs ci
and yi and outputs ci = 1 and xi, is referred to as a typical cell.
Before addition can take place, the accumulator must be loaded with X. This can be accomplished in
several ways. The easiest way is to first clear the accumulator using the asynchronous clear inputs on the
flip-flops, and then put the X data on the Y inputs to the adder and add to the accumulator in the normal
way. Alternatively, we could add multiplexers at the accumulator inputs so that we could select either the
Y input data or the adder output to load into the accumulator. This would eliminate the extra step of
clearing the accumulator but would add to the hardware complexity.
The following Figure shows a typical cell of the adder where the accumulator flip-flop can either be
loaded directly from yi or from the sum output (si).When Ld = 1 the multiplexer selects yi, and yi is loaded
into the accumulator flip-flop (xi) on the rising clock edge. When Ad = 1 and Ld = 0, the adder output (si)
is loaded into xi. The Ad and Ld signals are ORed together to enable the clock when either addition or
loading occurs. When Ad = Ld = 0, the clock is disabled and the accumulator outputs do not change.
4
18CS33
MODULE – 5
REGISTERS AND COUNTERS
A register consists of a group of flip-flops with a common clock input. Registers are commonly used to
store and shift binary data.
Counters are another simple type of sequential circuits. A counter is usually constructed from two or
more flip-flops which change states in a prescribed sequence when input pulses are received.
REGISTERS AND REGISTER TRANSFERS:
Several D flip-flops may be grouped together with a common clock to form a register (SEE THE
FOLLOWING Figure). Since each flip-flop can store one bit of information, this register can store four
bits of information. This register has a load signal that is ANDed with the clock.
When Load = 0, the register is not clocked, and it holds its present value. Load = 1, the clock signal (Clk)
is transmitted to the flip-flop clock inputs and the data applied to the D inputs will be loaded into the flip-
flops on the falling edge of the clock.
For example, if the Q outputs are 0000 (Q3 = Q2 = Q1 = Q0 = 0) and the data inputs are 1101 (D3 = 1,
D2 = 1, D1 = 0 and D0 = 1), after the falling edge of clock, Q will change from 0000 to 1101 as indicated
in the above Figure (The notation 0 → 1 at the flip-flop outputs indicates a change from 0 to 1).
The flip-flops in the register have asynchronous clear inputs that are connected to a common clear signal,
ClrN. The bubble at the clear inputs indicates that a logic 0 is required to clear the flip-flops. ClrN is
normally 1, and if it is changed momentarily to 0, the Q outputs of all four flip-flops will become 0.
Gating the clock with another signal can cause timing problems. If flip-flops with clock enable are
available, the register can be designed as shown in the following Figure (b).
1
, ANALOG AND DIGITAL ELECTRONICS
18CS33
The load signal is connected to all four CE inputs. When Load = 0, the clock is disabled and the register
holds its data. When Load = 1, the clock is enabled, and the data applied to the D inputs will be loaded
into the flip-flops, following the falling edge of the clock.
Figure (c) shows a symbol for the 4-bit register using bus notation for the D inputs and Q outputs. A
group of wires that perform a common function is often referred to as a bus. A heavy line is used to
represent a bus, and a slash with a number beside it indicates the number of bits in the bus.
Transferring data between registers is a common operation in digital systems. The following Figure
shows how data can be transferred from the output of one of two registers into a third register using tri-
state buffers.
If En = 1 and Load = 1, the output of register A is enabled onto the tri-state bus and the data in register A
will be stored in Q after the rising edge of the clock. If En = 0 and Load = 1, the output of register B will
be enabled onto the tri-state bus and stored in Q after the rising edge of the clock.
2
, ANALOG AND DIGITAL ELECTRONICS
18CS33
The following Figure (a) shows an integrated circuit register that contains eight D flip-flops with tri-state
buffers at the flip-flop outputs. These buffers are enabled when En = 0. A symbol for this 8-bit register is
shown in Figure (b).
The following Figure (c) shows how data can be transferred from one of four 8-bit registers into one of
two other registers. Registers A, B, C, and D are of the type shown in above Figure.
The outputs from these registers are all connected in parallel to a common tri-state bus. Registers G and H
are 8-bit D type registers (PIPO). The flip-flop inputs of registers G and H are also connected to the bus.
When EnA = 0, the tri-state outputs of register A are enabled onto the bus. If LdG = 1, these signals on
the bus are loaded into register G after the rising clock edge (or into register H if LdH = 1). Similarly, the
data in register B, C, or D is transferred to G (or H) when EnB, EnC, or EnD is 0, respectively and LdG =
1 (or LdH = 1). If LdG = LdH = 1, both G and H will be loaded from the bus. The four enable signals
may be generated by a decoder. The operation can be summarized as follows:
If EF = 00, A is stored in G (or H) If EF = 01, B is stored in G (or H).
If EF = 10, C is stored in G (or H) If EF = 11, D is stored in G (or H).
Note that 8 bits of data are transferred in parallel from register A, B, C, or D to register G or H. As an
alternative to using a bus with tri-state logic, eight 4-to-1 multiplexers could be used, but this would lead
to a more complex circuit.
3
, ANALOG AND DIGITAL ELECTRONICS
18CS33
Parallel Adder with Accumulator:
In computer circuits, it is frequently desirable to store one number in a register of flip-flops (called an
accumulator) and add a second number to it, leaving the result stored in the accumulator.
One way to build a parallel adder with an accumulator is to add a register to the adder as shown in the
following Figure.
Suppose that the number X = xn . . . x2x1 is stored in the accumulator. Then, the number Y = yn . . . y2y1 is
applied to the full adder inputs, and after the carry has propagated through the adders, the sum of X and Y
appears at the adder outputs. An add signal (Ad) is used to load the adder outputs into the accumulator
flip-flops on the rising clock edge. If si = 1, the next state of flip-flop xi will be 1. If si = 0, the next state
of flip-flop xi will be 0.Thus, xi+ = si, and if Ad = 1, the number X in the accumulator is replaced with the
sum of X and Y, following the rising edge of the clock.
Observe that the adder with accumulator is an iterative structure that consists of a number of identical
cells. Each cell contains a full adder and an associated accumulator flip-flop. Cell i, which has inputs ci
and yi and outputs ci = 1 and xi, is referred to as a typical cell.
Before addition can take place, the accumulator must be loaded with X. This can be accomplished in
several ways. The easiest way is to first clear the accumulator using the asynchronous clear inputs on the
flip-flops, and then put the X data on the Y inputs to the adder and add to the accumulator in the normal
way. Alternatively, we could add multiplexers at the accumulator inputs so that we could select either the
Y input data or the adder output to load into the accumulator. This would eliminate the extra step of
clearing the accumulator but would add to the hardware complexity.
The following Figure shows a typical cell of the adder where the accumulator flip-flop can either be
loaded directly from yi or from the sum output (si).When Ld = 1 the multiplexer selects yi, and yi is loaded
into the accumulator flip-flop (xi) on the rising clock edge. When Ad = 1 and Ld = 0, the adder output (si)
is loaded into xi. The Ad and Ld signals are ORed together to enable the clock when either addition or
loading occurs. When Ad = Ld = 0, the clock is disabled and the accumulator outputs do not change.
4
