ANALOG AND DIGITAL ELECTRONICS
18CS33
MODULE – 3
VHDL, LATCHES AND FLIP-FLOPS
INTROIDUCTION TO VHDL
The acronym VHDL stands for VHSIC-HDL (Very High Speed Integrated Circuit-Hardware Description
Language). VHDL is a hardware description language that is used to describe the behavior and structure
of digital systems. VHDL is a general-purpose hardware description language which can be used to
describe and simulate the operation of a wide variety of digital systems, ranging in complexity from a few
gates to an interconnection of many complex integrated circuits.
VHDL was originally developed to allow a uniform method for specifying digital systems. The VHDL
language became an IEEE standard in 1987, and it is widely used in industry. IEEE published a revised
VHDL standard in 1993.
VHDL can describe a digital system at several different levels—behavioral, data flow, and structural. For
example,
o A binary adder could be described at the behavioral level in terms of its function of adding two
binary numbers, without giving any implementation details.
o The same adder could be described at the data flow level by giving the logic equations for the
adder.
o Finally, the adder could be described at the structural level by specifying the interconnections of
the gates which make up the adder.
VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS:
In VHDL, a signal assignment statement has the form:
The expression is evaluated when the statement is executed, and the signal on the left side is scheduled to
change after delay. The square brackets indicate that after delay is optional. If after delay is omitted, then
the signal is scheduled to be updated after a delta delay, ∆ (infinitesimal delay). A VHDL signal is used
to describe a signal in a physical system. The VHDL language also includes variables similar to variables
in programming languages.
In general, VHDL is not case sensitive, that is, capital and lower case letters are treated the same by the
compiler and the simulator. Signal names and other VHDL identifiers may contain letters, numbers, and
the underscore character ( _ ). An identifier must start with a letter, and it cannot end with an underscore.
Thus, C123 and ab_23 are legal identifiers, but 1ABC and ABC_ are not. Every VHDL statement must be
terminated with a semicolon. Spaces, tabs, and carriage returns are treated in the same way. This means
that a VHDL statement can be continued over several lines, or several statements can be placed on one
line. In a line of VHDL code, anything following a double dash (--) is treated as a comment. Words such
1
, ANALOG AND DIGITAL ELECTRONICS
18CS33
as and, or, and after are reserved words (or keywords) which have a special meaning to the VHDL
compiler.
The gate circuit of the following Figure has five signals: A, B, C, D, and E. The symbol “ <= ” is the
signal assignment operator which indicates that the value computed on the right-hand side is assigned to
the signal on the left side.
Dataflow Description: The two assignment statements (given below) give a dataflow description of the
above circuit, where it is assumed that each gate has a 5-ns propagation delay. When these statements are
simulated, the first statement will be evaluated any time A or B changes, and the second statement will be
evaluated any time C or D changes. Suppose that initially A = 1, and B = C = D = E = 0; and if B changes
to 1 at time 0, C will change to 1 at time = 5 ns. Then, E will change to 1 at time = 10 ns.
C <= A and B after 5 ns;
E <= C or D after 5 ns;
VHDL signal assignment statements (as given above) are concurrent statements. The VHDL simulator
monitors the right side of each concurrent statement, and any time a signal changes, the expression on the
right side is immediately re-evaluated. The new value is assigned to the signal on the left side after an
appropriate delay. This is exactly the way the hardware works. Any time a gate input changes, the gate
output is recomputed by the hardware, and the output changes after the gate delay. Unlike a sequential
program, the order of the above concurrent statements is unimportant.
Behavioral Description: A behavioral description of the above circuit shown is
E <= D or (A and B);
Parentheses are used to specify the order of operator execution.
Structural Description: The above circuit shown can also be described using structural VHDL code. To
do so requires that a two-input AND-gate component and a two-input OR-gate component be declared
and defined.
Components may be declared and defined either in a library or within the architecture part of the VHDL
code. Instantiation statements are used to specify how components are connected. Each copy of a
component requires a separate instantiation statement to specify how it is connected to other components
and to the port inputs and outputs. An instantiation statement is a concurrent statement that executes
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, ANALOG AND DIGITAL ELECTRONICS
18CS33
anytime one of the input signals in its port map changes. The circuit shown is described by instantiating
the AND gate and the OR gate as follows:
Gate1: AND2 port map (A, B, D);
Gate2: OR2 port map (C, D, E);
The port map for Gate1 connects A and B to the AND-gate inputs, and it connects D to the AND-gate
output. Since an instantiation statement is concurrent, whenever A or B changes, these changes go to the
Gate1 inputs, and then the component computes a new value of D. Similarly, the second statement passes
changes in C or D to the Gate 2 inputs, and then the component computes a new value of E. This is
exactly how the real hardware works. (The order in which the instantiation statements appear is
irrelevant).
Instantiating a component is different than calling a function in a computer program. A function returns a
new value whenever it is called, but an instantiated component computes a new output value whenever its
input changes.
The following Figure shows an inverter with the output connected back to the input. If the output is „0‟,
then this „0‟ feeds back to the input and the inverter output changes to „1‟ after the inverter delay,
assumed to be 10 ns. Then, the „1‟ feeds back to the input, and the output changes to „0‟ after the inverter
delay. The signal CLK will continue to oscillate between „0‟ and „1‟, as shown in the waveform. The
corresponding concurrent VHDL statement will produce the same result. If CLK is initialized to „0‟, the
statement executes and CLK changes to „1‟ after 10 ns. Because CLK has changed, the statement
executes again, and CLK will change back to „0‟ after another 10 ns. This process will continue
indefinitely.
The following Figure shows three gates that have the signal A as a common input and the corresponding
VHDL code. The three concurrent statements execute simultaneously whenever A changes, just as the
three gates start processing the signal change at the same time. However, if the gates have different
delays, the gate outputs can change at different times. If the gates have delays of 2 ns, 1 ns, and 3 ns,
respectively, and A changes at time 5 ns, then the gate outputs D, E, and F can change at times 7 ns, 6 ns,
and 8 ns, respectively. However, if no delays were specified, then D, E, and F would all be updated at
time 5 + ∆.
3
18CS33
MODULE – 3
VHDL, LATCHES AND FLIP-FLOPS
INTROIDUCTION TO VHDL
The acronym VHDL stands for VHSIC-HDL (Very High Speed Integrated Circuit-Hardware Description
Language). VHDL is a hardware description language that is used to describe the behavior and structure
of digital systems. VHDL is a general-purpose hardware description language which can be used to
describe and simulate the operation of a wide variety of digital systems, ranging in complexity from a few
gates to an interconnection of many complex integrated circuits.
VHDL was originally developed to allow a uniform method for specifying digital systems. The VHDL
language became an IEEE standard in 1987, and it is widely used in industry. IEEE published a revised
VHDL standard in 1993.
VHDL can describe a digital system at several different levels—behavioral, data flow, and structural. For
example,
o A binary adder could be described at the behavioral level in terms of its function of adding two
binary numbers, without giving any implementation details.
o The same adder could be described at the data flow level by giving the logic equations for the
adder.
o Finally, the adder could be described at the structural level by specifying the interconnections of
the gates which make up the adder.
VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS:
In VHDL, a signal assignment statement has the form:
The expression is evaluated when the statement is executed, and the signal on the left side is scheduled to
change after delay. The square brackets indicate that after delay is optional. If after delay is omitted, then
the signal is scheduled to be updated after a delta delay, ∆ (infinitesimal delay). A VHDL signal is used
to describe a signal in a physical system. The VHDL language also includes variables similar to variables
in programming languages.
In general, VHDL is not case sensitive, that is, capital and lower case letters are treated the same by the
compiler and the simulator. Signal names and other VHDL identifiers may contain letters, numbers, and
the underscore character ( _ ). An identifier must start with a letter, and it cannot end with an underscore.
Thus, C123 and ab_23 are legal identifiers, but 1ABC and ABC_ are not. Every VHDL statement must be
terminated with a semicolon. Spaces, tabs, and carriage returns are treated in the same way. This means
that a VHDL statement can be continued over several lines, or several statements can be placed on one
line. In a line of VHDL code, anything following a double dash (--) is treated as a comment. Words such
1
, ANALOG AND DIGITAL ELECTRONICS
18CS33
as and, or, and after are reserved words (or keywords) which have a special meaning to the VHDL
compiler.
The gate circuit of the following Figure has five signals: A, B, C, D, and E. The symbol “ <= ” is the
signal assignment operator which indicates that the value computed on the right-hand side is assigned to
the signal on the left side.
Dataflow Description: The two assignment statements (given below) give a dataflow description of the
above circuit, where it is assumed that each gate has a 5-ns propagation delay. When these statements are
simulated, the first statement will be evaluated any time A or B changes, and the second statement will be
evaluated any time C or D changes. Suppose that initially A = 1, and B = C = D = E = 0; and if B changes
to 1 at time 0, C will change to 1 at time = 5 ns. Then, E will change to 1 at time = 10 ns.
C <= A and B after 5 ns;
E <= C or D after 5 ns;
VHDL signal assignment statements (as given above) are concurrent statements. The VHDL simulator
monitors the right side of each concurrent statement, and any time a signal changes, the expression on the
right side is immediately re-evaluated. The new value is assigned to the signal on the left side after an
appropriate delay. This is exactly the way the hardware works. Any time a gate input changes, the gate
output is recomputed by the hardware, and the output changes after the gate delay. Unlike a sequential
program, the order of the above concurrent statements is unimportant.
Behavioral Description: A behavioral description of the above circuit shown is
E <= D or (A and B);
Parentheses are used to specify the order of operator execution.
Structural Description: The above circuit shown can also be described using structural VHDL code. To
do so requires that a two-input AND-gate component and a two-input OR-gate component be declared
and defined.
Components may be declared and defined either in a library or within the architecture part of the VHDL
code. Instantiation statements are used to specify how components are connected. Each copy of a
component requires a separate instantiation statement to specify how it is connected to other components
and to the port inputs and outputs. An instantiation statement is a concurrent statement that executes
2
, ANALOG AND DIGITAL ELECTRONICS
18CS33
anytime one of the input signals in its port map changes. The circuit shown is described by instantiating
the AND gate and the OR gate as follows:
Gate1: AND2 port map (A, B, D);
Gate2: OR2 port map (C, D, E);
The port map for Gate1 connects A and B to the AND-gate inputs, and it connects D to the AND-gate
output. Since an instantiation statement is concurrent, whenever A or B changes, these changes go to the
Gate1 inputs, and then the component computes a new value of D. Similarly, the second statement passes
changes in C or D to the Gate 2 inputs, and then the component computes a new value of E. This is
exactly how the real hardware works. (The order in which the instantiation statements appear is
irrelevant).
Instantiating a component is different than calling a function in a computer program. A function returns a
new value whenever it is called, but an instantiated component computes a new output value whenever its
input changes.
The following Figure shows an inverter with the output connected back to the input. If the output is „0‟,
then this „0‟ feeds back to the input and the inverter output changes to „1‟ after the inverter delay,
assumed to be 10 ns. Then, the „1‟ feeds back to the input, and the output changes to „0‟ after the inverter
delay. The signal CLK will continue to oscillate between „0‟ and „1‟, as shown in the waveform. The
corresponding concurrent VHDL statement will produce the same result. If CLK is initialized to „0‟, the
statement executes and CLK changes to „1‟ after 10 ns. Because CLK has changed, the statement
executes again, and CLK will change back to „0‟ after another 10 ns. This process will continue
indefinitely.
The following Figure shows three gates that have the signal A as a common input and the corresponding
VHDL code. The three concurrent statements execute simultaneously whenever A changes, just as the
three gates start processing the signal change at the same time. However, if the gates have different
delays, the gate outputs can change at different times. If the gates have delays of 2 ns, 1 ns, and 3 ns,
respectively, and A changes at time 5 ns, then the gate outputs D, E, and F can change at times 7 ns, 6 ns,
and 8 ns, respectively. However, if no delays were specified, then D, E, and F would all be updated at
time 5 + ∆.
3
