BXE End-Sem Question
Bank
Unit 3 • unit 4 • Unit 5 • Unit 6
Unit No:- 03
1. State and prove De-Morgan’s Theorem
Two of the theorems were suggested by De Morgan that are extremely useful for Boolean Algebra. These two
theorems have been discussed below in this article:
Theorem 1
• The LHS (left-hand side) of this theorem represents the NAND gate that has inputs A and B. On the other
hand, the RHS (right-hand side) of this theorem represents the OR gate that has inverted inputs.
• The OR gate here is known as a Bubbled OR.
Here is a table that shows the verification of the first theorem of De Morgan:
https://msha.ke/btechnotes pg. 1
,Theorem 2
• The left-hand side of this theorem represents the NOR gate that has inputs A and B. On the other hand,
the right-hand side represents the AND gate that has inverted inputs.
• The AND gate here is known as a Bubbled AND.
Here is a table that shows the verification of the second theorem of De Morgan:
https://msha.ke/btechnotes pg. 2
, 2. Design and implement full adder circuit. Write the expressions for sum and Cout.
A full adder circuit is a combinational logic circuit that adds three input bits: A, B, and Cin (carry-in) and produces
two outputs: Sum (S) and Cout (carry-out). The Sum output represents the binary sum of the three inputs, while
the Cout output represents the carry generated by the addition.
Here are the expressions for the Sum (S) and Cout (Cout) outputs of a full adder:
Sum (S) = A ⊕ B ⊕ Cin
Cout = (A ∧ B) ∨ (Cin ∧ (A ⊕ B))
To implement a full adder circuit, we can use logic gates such as XOR (⊕), AND (∧), and OR (∨). Here's the circuit
diagram for a full adder:
In the circuit diagram, the XOR gates compute the sum (S), while the AND and OR gates compute the carry-out
(Cout).
To summarize the circuit operation:
- The XOR gates calculate the sum of the inputs A, B, and Cin.
https://msha.ke/btechnotes pg. 3
, - The AND gate generates a carry when both A and B are high.
- The OR gate combines the carry from the AND gate with the carry-in (Cin).
By implementing this circuit, you can perform binary addition by providing the inputs A, B, and Cin, and obtain the
outputs Sum (S) and Cout.
3. What is Flip flop? Explain SR FF, J-K FF.
A flip-flop is a sequential logic circuit element that can store and remember a single bit of information. It is
widely used in digital electronics and is fundamental for building registers, counters, and other sequential
circuits. Two commonly used types of flip-flops are the SR (Set-Reset) flip-flop and the J-K flip-flop.
1. SR Flip-Flop:
The SR flip-flop, also known as the Set-Reset flip-flop, has two inputs: S (Set) and R (Reset). It has two stable
states: Set state (Q = 1) and Reset state (Q = 0). The behavior of an SR flip-flop can be summarized as follows:
- When both S and R inputs are low (0), the current state is maintained.
- When S = 1 and R = 0, the flip-flop is set, and Q = 1.
- When S = 0 and R = 1, the flip-flop is reset, and Q = 0.
- When both S and R inputs are high (1), it creates an invalid state and should be avoided.
SR flip-flops can be implemented using NAND or NOR gates. Here's the truth table and logic diagram for an SR
flip-flop:
2. J-K Flip-Flop:
The J-K flip-flop is an extension of the SR flip-flop and overcomes the invalid state by adding a feedback
mechanism. It has two inputs: J (set) and K (reset), along with a clock input (CLK). The J-K flip-flop has two
https://msha.ke/btechnotes pg. 4
Bank
Unit 3 • unit 4 • Unit 5 • Unit 6
Unit No:- 03
1. State and prove De-Morgan’s Theorem
Two of the theorems were suggested by De Morgan that are extremely useful for Boolean Algebra. These two
theorems have been discussed below in this article:
Theorem 1
• The LHS (left-hand side) of this theorem represents the NAND gate that has inputs A and B. On the other
hand, the RHS (right-hand side) of this theorem represents the OR gate that has inverted inputs.
• The OR gate here is known as a Bubbled OR.
Here is a table that shows the verification of the first theorem of De Morgan:
https://msha.ke/btechnotes pg. 1
,Theorem 2
• The left-hand side of this theorem represents the NOR gate that has inputs A and B. On the other hand,
the right-hand side represents the AND gate that has inverted inputs.
• The AND gate here is known as a Bubbled AND.
Here is a table that shows the verification of the second theorem of De Morgan:
https://msha.ke/btechnotes pg. 2
, 2. Design and implement full adder circuit. Write the expressions for sum and Cout.
A full adder circuit is a combinational logic circuit that adds three input bits: A, B, and Cin (carry-in) and produces
two outputs: Sum (S) and Cout (carry-out). The Sum output represents the binary sum of the three inputs, while
the Cout output represents the carry generated by the addition.
Here are the expressions for the Sum (S) and Cout (Cout) outputs of a full adder:
Sum (S) = A ⊕ B ⊕ Cin
Cout = (A ∧ B) ∨ (Cin ∧ (A ⊕ B))
To implement a full adder circuit, we can use logic gates such as XOR (⊕), AND (∧), and OR (∨). Here's the circuit
diagram for a full adder:
In the circuit diagram, the XOR gates compute the sum (S), while the AND and OR gates compute the carry-out
(Cout).
To summarize the circuit operation:
- The XOR gates calculate the sum of the inputs A, B, and Cin.
https://msha.ke/btechnotes pg. 3
, - The AND gate generates a carry when both A and B are high.
- The OR gate combines the carry from the AND gate with the carry-in (Cin).
By implementing this circuit, you can perform binary addition by providing the inputs A, B, and Cin, and obtain the
outputs Sum (S) and Cout.
3. What is Flip flop? Explain SR FF, J-K FF.
A flip-flop is a sequential logic circuit element that can store and remember a single bit of information. It is
widely used in digital electronics and is fundamental for building registers, counters, and other sequential
circuits. Two commonly used types of flip-flops are the SR (Set-Reset) flip-flop and the J-K flip-flop.
1. SR Flip-Flop:
The SR flip-flop, also known as the Set-Reset flip-flop, has two inputs: S (Set) and R (Reset). It has two stable
states: Set state (Q = 1) and Reset state (Q = 0). The behavior of an SR flip-flop can be summarized as follows:
- When both S and R inputs are low (0), the current state is maintained.
- When S = 1 and R = 0, the flip-flop is set, and Q = 1.
- When S = 0 and R = 1, the flip-flop is reset, and Q = 0.
- When both S and R inputs are high (1), it creates an invalid state and should be avoided.
SR flip-flops can be implemented using NAND or NOR gates. Here's the truth table and logic diagram for an SR
flip-flop:
2. J-K Flip-Flop:
The J-K flip-flop is an extension of the SR flip-flop and overcomes the invalid state by adding a feedback
mechanism. It has two inputs: J (set) and K (reset), along with a clock input (CLK). The J-K flip-flop has two
https://msha.ke/btechnotes pg. 4
