digital circuit

Part One - Verilog

Purpose:

 Learn the basics of structural Verilog Syntax.
 Learn to create a new project using Verilog.
 Learn to simulate the behavior of the universal (NAND/NOR) gates using
DigitalJS Online tool.

Apply the following steps to create a Verilog file, write a module, and
then simulate the model by creating signal waveforms for each exercise.

A. Design:
a) Create a new Verilog HDL design file and Save it (.v).
b) Create a module having the same name as the project name.
c) Determine the number of inputs, outputs, and wires to build the circuit.
d) Write your code using structural Verilog.
e) Check the code for syntax errors.

B. Simulation:
a) Open the https://digitaljs.tilk.eu/ website.
b) Load the Verilog file previously created by selecting “Load from File” tab
and select the “*.v” file.
c) Press the “Synthesize and simulate” button, a diagram of the circuit will be
shown on the right panel.
d) Check the wave alternations for all the possible combinations of inputs, and
their output.
e) Sketch the wave form with the different input combinations and output
result, then draw the truth table of each gate.

Exercises:

, 1. Write a module that implements the functions Q and F of the circuit
diagrams given below. Check the two outputs Q and F. Are they equivalent
experimentally? Prove it using Boolean algebra and show your work.




Solution:

Q and F are equivalent
module nands(A,B,Q,F);

input A,B;

output Q,F;

wire c,d;

nand(c,A,A);

nand(d,B,B);

nand(Q,c,d);

or(F,A,B);

endmodule



2. Write a module that implements the functions X, Y, Q and QX of the circuit
diagrams given below. Then, Compare the outputs Q and Y as well as X and
QX. Are they equivalent experimentally? Prove it using Boolean algebra and
show your work.